Problems with using to_stdlogicvector()

[SR]

Hi,

On trying to compile the following program, I keep getting errors where
I am using to_stdlogicvector(). I am using bit_vectors since I plan to
write a test bench that reads and writes to a file.

Thanks and I appreciate the consideration.

Mani


library IEEE;
use IEEE.std_logic_1164.all;

entity counter is
port (
reset,ck: in bit;
din : in bit_vector(7 downto 0);
count : out bit_vector(7 downto 0));
end entity counter;

architecture behavioral of counter is
signal cnt: bit_vector(7 downto 0);
begin

counter : process(ck,reset,din) is
variable temp: std_logic_vector(7 downto 0);
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

if reset = '1' then
cnt <= "00000000";
elsif (rising_edge(clk)) then
if cnt = "11111111" then
cnt <= "00000000";
else
temp :=to_stdlogicvector(cnt);
temp := temp+1;
cnt <= to_bitvector(temp);
end if;

end if;
count<= cnt;
end process counter;


end architecture behavioral;

 

[Just an Illusion]

Hi SR,

It seems you have many differents issues ;-)

SR wrote:

...
variable clk: std_logic;
begin
clk:= to_stdlogicvector(ck);

Is it not ?
clk := to_stdlogic(ck);

...
temp :=to_stdlogicvector(cnt);

Here it missing logic vector sizes

temp (7 downto 0) := to_stdlogicvector(cnt (7 downto 0));

...
cnt <= to_bitvector(temp);

Same remark
cnt (7 downto 0) := to_bitvector (temp (7 downto 0) );


But why continue to use bit, if you use std_logic locally ?
If you change your bit and bit_vector to std_logic and std_logic_vector,
you have no more problems ;-)

Rgrds,
JaI