Problems with timing constraints

[salimbaba]

Hey, I am facing difficulties in dealing with timing constraints. I hav
different sections of my logic running on different clocks. All clocks hav
their own timing constraints ,PERIOD and OFFSET IN BEFORE..
the problem is that when i change one of the constraints of one interfac
on one clock it also effects the other interface on the 2nd clock wit
seperate constrainsts...this varies from run to run,,,,i have als
generated the verbose timing and par report....

there is not much difference in the timing values(Slack,Setup,Hold) betwee
the working bit files and the non working bit files..can anyone plz help


there are the constraints


NET "mclk" TNM_NET = "mclk"; TIMESPEC "TS_mclk" = PERIOD "mclk" 40 ns HIG
50 %;

NET "mclk" TNM_NET = "mclk";
TIMESPEC "TS_mclk" = PERIOD "mclk" 40 ns HIGH 50 %;


NET "tx_clk_1" TNM_NET = "tx_clk_1";
TIMESPEC "TS_tx_clk_1" = PERIOD "tx_clk_1" 40 ns HIGH 50 %;

INST "write_" TNM = "mclk_pads";
INST "read_" TNM = "mclk_pads";
INST "cs" TNM = "mclk_pads";

INST "d1_stream_data_in_pos_A" TNM = "tx_clk_1_pads";
INST "d1_stream_data_in_neg_A" TNM = "tx_clk_1_pads";
INST "d1_stream_clk_in_pos_A" TNM = "tx_clk_1_pads";

TIMEGRP "mclk_pads" OFFSET = IN 27 ns BEFORE "mclk" ;
TIMEGRP "tx_clk_1_pads" OFFSET = IN 25 ns BEFORE "tx_clk_1" ;
ITS IN the last two lines that if i change OFFESET for tx_clk_1 pads i
makes my mclk_pads interface to go hay wire

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