Problems with synchronization

[ALuPin]

Hi people out there,

I want to post my following problem hoping that somebody has an answer
and maybe somebody can use this post later when googling.


To the problem:

First clock : 90MHz
Second clock : 30MHz
The clocks can be out of phase or they can be in phase to each other.

My question:
Is the change from s_wait to s_state1 performed
without any problems ? IMO SETUP and HOLD violations can erase
which under circumstances can lead to an unscheduled change.
What possiblities do I have to avoid that ?
Any synchronization method should consume little amount of time.

Thanks in advance.

Rgds
André

-- Generate_ack is synchronous to Clk_90
process(Reset, Clk_90)
begin
if Reset='1' then
l_enable_generate_ack <= '0';
elsif rising_edge(Clk_90) then
l_enable_generate_ack <= l_enable_generate_ack;

if Generate_ack='1' then
l_enable_generate_ack <= '1';
end if;
if l_eop_sync='1' then
l_enable_generate_ack <= '0';
end if;
end if;
end process;

process(Reset, Clk_30)
begin
if Reset='1' then
l_state <= s_wait;
l_eop <= '0';
elsif rising_edge(Clk_30) then
l_state <= l_state;
l_eop <= '0';

case l_state is

when s_wait =>
if l_enable_generate_ack='1' then
l_state <= s_state1;
end if;
when s_state1 =>
if other_condition_30MHz_domain='1' then
l_state <= s_state2;
end if;
when s_state2 =>
l_state <= s_state3;
l_eop <= '1';
when s_state3 =>
l_state <= s_state4;
when s_state4 =>
l_state <= s_state5;
when s_state5 =>
l_state <= s_wait;
end if;
end process;

l_eop_sync is the synchronized l_eop from the 30MHz into the 90MHz
clock domain.

 

[Thomas Reinemann]

ALuPin wrote:

l_enable_generate_ack <= l_enable_generate_ack;
l_state <= l_state;

What is the intention of this both lines? I assume a signal value will be
unchanged if it isn't assigned a new value.

Bye Tom

 

[Pieter Hulshoff]

ALuPin wrote:

Is the change from s_wait to s_state1 performed
without any problems ? IMO SETUP and HOLD violations can erase
which under circumstances can lead to an unscheduled change.

No, it is not performed without problems. The signal l_enable_generate_ack
needs to be synchronized to the 30 MHz domain before using it. Otherwise
you can get very unexpected behaviour in your eventual chip.

What possiblities do I have to avoid that ?
Any synchronization method should consume little amount of time.

Clock the signal twice on the 30 MHz signal, and use that signal instead.
You can also opt for clocking three times, and use the 2nd and 3rd FF to do
edge detection.

Regards,

Pieter Hulshoff