Problems with pin assignment file in Encounter Test

[Hannes]

Hello,

I need to write a pin assignment file for Encounter Test.
and I found the following description in the forum.

My problem is, that I don't understand the meaning of the different
levels (0,1,-,+, Z) in this context

Does for example

assign pin=tm_clk test_function= -ES; # test clock


mean that the pin tm_clk is defined as a shift + system clock negative
edge triggered?



But if so, what means

assign pin=se test_function= +SE; # shift_enable

?

Here se is not edge triggered, but has a "+" as level assigment?



Best regards

Hannes


diablo wrote the 1st Dec.2010 :



Pin assignment file is generated by RTL compiler when doing DFT
synthesis flow. At the end of the sythesis flow, you can run
"write_et_atpg" to generate those files needed by ET.

If its not available in your case, you can easily write one up. Pin
assignment need three information for every pin assigned for ATPG. The
first is pin name, second the pin functionality and third the levels at
that pin.




Pin functions:

TI – Test Inhibit - set throughout test application
TC – Test Constraint – set during capture cycles
SE – Scan Enable – set during shift
SI, SO – Scan Ins/Outs
SC – non shift system clock (edge triggered or level sensitive)
ES – shift + system clock (edge triggered)
EC – shift only clock (edge triggered)

Levels

- , 0
+, 1
Z

For an example,

assign pin=se test_function= +SE; # shift_enable

assign pin=tm_clk test_function= -ES; # test clock

assign pin=tm test_function = +TI; # test mode

Regards.