Problems with ModelSim II

[Peter]

Hello all,

I am a absolute newby trying really hard to grasp this Verilog thing and am
having problems with getting my first simple module to compile and work with
ModelSim II - Starter Xilinx edition.

Here is the module:

module counter(clk, cnt, count);
input clk;
output [3:0]cnt;
output [3:0]count;
reg [3:0]count;

always@(posedge clk)
begin
count <= (count + 1) % 11;
cnt = count;
end

endmodule

When I attempt to compile the above module, it tells me "illegal use of cnt"
in the line <cnt = count;>
If I comment this line out, it compiles OK, but when I test the module using
a clock defined in the ModelSim GUI, the count register does not change it's
starting value from xxxx. I have stepped the simulation and it definately
executes the line where count is supposed to update.

Can anyone give me any hints? (I'm now getting nowhere)

Regards, Peter

 

[m]

On Fri, 29 Jul 2005 13:29:15 +0800, "Peter" <peterw@nowhere.com.au>
wrote:

Hello all,

I am a absolute newby trying really hard to grasp this Verilog thing and am
having problems with getting my first simple module to compile and work with
ModelSim II - Starter Xilinx edition.

Here is the module:

module counter(clk, cnt, count);
input clk;
output [3:0]cnt;
output [3:0]count;
reg [3:0]count;

always@(posedge clk)
begin
count <= (count + 1) % 11;
cnt = count;
end

endmodule

When I attempt to compile the above module, it tells me "illegal use of cnt"
in the line <cnt = count;
If I comment this line out, it compiles OK, but when I test the module using
a clock defined in the ModelSim GUI, the count register does not change it's
starting value from xxxx. I have stepped the simulation and it definately
executes the line where count is supposed to update.

Can anyone give me any hints? (I'm now getting nowhere)

Regards, Peter

I am not sure why you need the cnt but the problem is that because you
don't have a reg declaration for cnt, its type is net and you can't
assign to a net in an always block. If you want another name for count
you can say:
assign cnt = count;
outside the always block. If you want a delayed copy of the count, you
need to add
reg [3:0] cnt;
to your design. If this is what you want, it is also advisable to
write:
cnt <= count;
instead of the blocking statement although as it currently stands,
there is no difference.

As you your second problem, it's happening because count has a default
value of 4'bxxxx and x+1 is also x so its value never changes from the
default. Without making your design more complicated than necessary,
you can just add
initial count = 0;
which should fix it. Of course this is not synthesizable but you'll
have to cross that bridge when you get to it (ie you need a reset on
the count variable).

Hope this helps.

 

[Peter]

"mk" <kal*@dspia.*comdelete> wrote in message
news:nsije1pagd3ue4vfljdl57g385d6oglr56@4ax.com...

On Fri, 29 Jul 2005 13:29:15 +0800, "Peter" <peterw@nowhere.com.au
wrote:

Hello all,

I am a absolute newby trying really hard to grasp this Verilog thing and
am
having problems with getting my first simple module to compile and work
with
ModelSim II - Starter Xilinx edition.

Here is the module:

module counter(clk, cnt, count);
input clk;
output [3:0]cnt;
output [3:0]count;
reg [3:0]count;

always@(posedge clk)
begin
count <= (count + 1) % 11;
cnt = count;
end

endmodule

When I attempt to compile the above module, it tells me "illegal use of
cnt"
in the line <cnt = count;
If I comment this line out, it compiles OK, but when I test the module
using
a clock defined in the ModelSim GUI, the count register does not change
it's
starting value from xxxx. I have stepped the simulation and it definately
executes the line where count is supposed to update.

Can anyone give me any hints? (I'm now getting nowhere)

Regards, Peter


I am not sure why you need the cnt but the problem is that because you
don't have a reg declaration for cnt, its type is net and you can't
assign to a net in an always block. If you want another name for count
you can say:
assign cnt = count;
outside the always block. If you want a delayed copy of the count, you
need to add
reg [3:0] cnt;
to your design. If this is what you want, it is also advisable to
write:
cnt <= count;
instead of the blocking statement although as it currently stands,
there is no difference.

As you your second problem, it's happening because count has a default
value of 4'bxxxx and x+1 is also x so its value never changes from the
default. Without making your design more complicated than necessary,
you can just add
initial count = 0;
which should fix it. Of course this is not synthesizable but you'll
have to cross that bridge when you get to it (ie you need a reset on
the count variable).

Hope this helps.

Yes, that all makes sense although it was not made very clear in the
tutorial I am using for guidance.
I understand the need for a counter reset signal later on.

Many thanks for your reply.
Regards, Peter

 

[Andy Peters]

Peter wrote:

I am a absolute newby trying really hard to grasp this Verilog thing and am
having problems with getting my first simple module to compile and work with
ModelSim II - Starter Xilinx edition.

Here is the module:

module counter(clk, cnt, count);
input clk;
output [3:0]cnt;
output [3:0]count;
reg [3:0]count;

always@(posedge clk)
begin
count <= (count + 1) % 11;
cnt = count;
end

endmodule

When I attempt to compile the above module, it tells me "illegal use of cnt"
in the line <cnt = count;

You need to buy a good Verilog book. Your question would have been
answered already!

The complaint arises because the output cnt is implicitly declared as
a(n array of) wire(s). You can't assign to a wire in an always block.
Hence, the error message.

If I comment this line out, it compiles OK, but when I test the module using
a clock defined in the ModelSim GUI, the count register does not change it's
starting value from xxxx. I have stepped the simulation and it definately
executes the line where count is supposed to update.

Ask yourself: "What is the value of count at time zero (when the
simulation starts)?" That clue should be sufficient.

-a