Problems with modelsim and conditional generate statement

[ArAgost]

Hi everybody, I'm having some problems with a conditional generate
statement, and I'm having some bad time trying to figure out the
reason, mainly because I'm quite a VHDL newbie :|

Having to instantiate several (70 and up depending on a generic)
components, I quickly found out the necessity of a generate statement.
Following many examples I found on books and websites, I also created
the necessary vectors to carry the values between each instance.

Here is the code:

entity Filler is
PORT(
tavolaS : IN table;
l : IN wordkey;
tavolaSmischiata : OUT table
);
end Filler;

architecture Fill of Filler is

Component mix IS
PORT(
i : IN integer;
j : IN integer;
A : IN word;
B : IN word;
s : IN table;
l : IN wordkey;

io : OUT integer;
jo : OUT integer;
Ao : OUT word;
Bo : OUT word;
So : OUT table;
Lo : OUT wordkey
);
end COMPONENT;

SIGNAL iuso : intarray := (others=>0);
SIGNAL juso : intarray := (others=>0);
SIGNAL Auso : wordarray :=
(others=>"00000000000000000000000000000000");
SIGNAL Buso : wordarray :=
(others=>"00000000000000000000000000000000");
SIGNAL nulltable : table :=
(others=>"00000000000000000000000000000000");
SIGNAL suso : tablearray := (others=>nulltable);
SIGNAL nullwordkey : wordkey := (others =>
"00000000000000000000000000000000");
SIGNAL luso : wordkeyarray := (others=>nullwordkey);

begin
suso(0) <= tavolaS;
luso(0) <= l;

g1: for cont in 0 to (f-1) GENERATE

primo: if cont = (0) generate
comp: mix port map (0, 0, "00000000000000000000000000000000",
"00000000000000000000000000000000", tavolaS, l, iuso(1), juso(1),
Auso(1), Buso(1), suso(1), luso(1));
end generate primo;

altro: if cont > (0) generate
comp: mix port map (iuso(cont), juso(cont), Auso(cont), Buso(cont),
suso(cont), luso(cont), iuso(cont+1), juso(cont+1), auso(cont+1),
buso(cont+1), suso(cont+1), luso(cont+1));
end generate altro;


end generate g1;

tavolaSmischiata <= suso(f);

end Fill;


Should be pretty self-explanatory ("word" is a standard logic vector,
"table" and "wordkey" are word arrays). If I go and simulate this in
modelsim, I will get... well, loads of cr*p. Integers will get values
like -2121893, and pretty much anything else will be U. However if I
modify the generate block to instantiate a single component (*not*
necessarily the first one) it all works like a charm. I don't really
think the problem is anywhere else since when this problem is not
occurring everything else works fine.
Is this caused by a bad conditional generate? Is it a port map problem?
Did I do something wrong with the helper arrays? Should I quit this and
begin teaching basketball to shrimps?

Any help will be more than appreciated.

Thanks in advance,

bye, A.