problems with `include and other related stuff

[DW]

Has anyone had any trouble using `include in Altera and/or Modelsim? I have
a file in which a constant is `defined. The synthesizer will not accept the
constant even though it does appear to be able to `include the file in which
it is defined. I tried using a `define directly in the file but had the
same result.

What I want to do is to pass pipeline delay values back up the heirarchy of
my design, such that the pipeline delay value at the top of the design is
automatically adjusted if I alter something at a lower level. I thought
about using `include files (one for each Verilog module) to communicate this
information, but I had the problems mentioned above.

I then thought that perhaps I can use parameters as demonstrated below:

module1.v
=======
parameter module1_delay= n + module2_instance.module2_delay;

module2 module2_instance(...)

module2.v
=======
parameter module2_delay= m + module3_instance.module3_delay;

module3 module3_instance(...)

module3.v
=======
parameter module3_delay= p;

and so on. Is this a good idea?- it seems to be accepted by Quartus2 but
Modelsim complains that
"# ** Error: ../library/modulex.v(59): parameter value must be constant"

Has anyone any suggestions?

Thanks.

 

[DW]

"DW" <dave_wooff@hotmail.com> wrote in message
news:cas50f$nnn$1$830fa795@news.demon.co.uk...

Has anyone had any trouble using `include in Altera and/or Modelsim? I
have
a file in which a constant is `defined. The synthesizer will not accept
the
constant even though it does appear to be able to `include the file in
which
it is defined. I tried using a `define directly in the file but had the
same result.

What I want to do is to pass pipeline delay values back up the heirarchy
of
my design, such that the pipeline delay value at the top of the design is
automatically adjusted if I alter something at a lower level. I thought
about using `include files (one for each Verilog module) to communicate
this
information, but I had the problems mentioned above.

I then thought that perhaps I can use parameters as demonstrated below:

module1.v
=======
parameter module1_delay= n + module2_instance.module2_delay;

module2 module2_instance(...)

module2.v
=======
parameter module2_delay= m + module3_instance.module3_delay;

module3 module3_instance(...)

module3.v
=======
parameter module3_delay= p;

and so on. Is this a good idea?- it seems to be accepted by Quartus2 but
Modelsim complains that
"# ** Error: ../library/modulex.v(59): parameter value must be constant"

Has anyone any suggestions?

Thanks.

Sorry everyone,
I found out that the accent ` is required on the definition wherever it is
used.
DW.