Problems with forcing a net

Has anyone ever seen a force on a net working it's way both up and down
the design hierarchy.

For example, consider the following module located somewhere in a
design hierarchy:

module temp(VSS);
input VSS;
supply0 VSS;

mod_temp2 temp2(.signal({VSS, VSS, VSS, VSS}))
endmodule


When I do a force on the net called signal in the temp2 instance to
4'b0101, instead of seeing that in the temp2 instance and below, VSS
turns to an X and signal turns to 4'bXXXX.

My suspicion is that the force on signal is working it's way up the
design hierarchy so the simulator tries to apply both a 0 and a 1 to
VSS resulting in an X. This then causes signal to be 4'bXXXX for some
reason.

I can't seem to reproduce this condition when I try to make a simple
testcase. This only seems to be a problem with the specific netlist
that I am working with.

Any ideas? Has anyone ever seen this before?

Thanks.

 

Do you have to declare VSS as "supply0"?
Try following: Comment that line "supply0 VSS;" and let us know what
happens.

Utku.

samirshah1983@gmail.com wrote:

Has anyone ever seen a force on a net working it's way both up and down
the design hierarchy.

For example, consider the following module located somewhere in a
design hierarchy:

module temp(VSS);
input VSS;
supply0 VSS;

mod_temp2 temp2(.signal({VSS, VSS, VSS, VSS}))
endmodule


When I do a force on the net called signal in the temp2 instance to
4'b0101, instead of seeing that in the temp2 instance and below, VSS
turns to an X and signal turns to 4'bXXXX.

My suspicion is that the force on signal is working it's way up the
design hierarchy so the simulator tries to apply both a 0 and a 1 to
VSS resulting in an X. This then causes signal to be 4'bXXXX for some
reason.

I can't seem to reproduce this condition when I try to make a simple
testcase. This only seems to be a problem with the specific netlist
that I am working with.

Any ideas? Has anyone ever seen this before?

Thanks.

 

samirshah1983@gmail.com wrote:

Has anyone ever seen a force on a net working it's way both up and down
the design hierarchy.

This is normal behavior for Verilog. Most simulator implementations do
what is called "port collapsing". When you have a simple enough
connection across a port, it collapses the nets on both sides of the
port into a single net. This is done for performance, and to match the
behavior of Verilog-XL, which did this. Also, it is more like real
hardware behavior. Real wire connections are not unidirectional. In
real hardware, the 4 nets of your example are all a single conductor,
and will all have the same value.

My suspicion is that the force on signal is working it's way up the
design hierarchy so the simulator tries to apply both a 0 and a 1 to
VSS resulting in an X. This then causes signal to be 4'bXXXX for some
reason.

I would have expected that the bits of the force would be applied in
some order, and each one would supercede the prior one, leaving you
with a 0 or 1 at the end. However, I can imagine that some
implementation might do what you are describing.