Problems with device

A

ALuPin

Guest
Hi newsgroup people,

maybe someone can help me with regard to the following problem:

I am using an Altera Cyclone Device EP1C12F256C7.

When I program it via JTAG (I am not able to program it via Serial Configuration
Device yet) the PLL I instantiated in the MegaWizard does run if the PLL
does not have a reset input.

I have programmed a little design, some counters which are resetted.
It doesn't matter whether the counters are resetted or not I cannot see
anything going on at the debug pins of my FPGA.

So the question is what goes wrong.

I mean if it was a basic problem the PLL would not run.
If it was exclusevely an reset problem the counters WITHOUT reset would run
but they do not!

I have a watchdog which produces an asynchronous reset but then it does
not get the trigger signal out of the FPGA so that the watchdog resets
periodically. The trigger signal I generate in the FPGA is depedent on
the counters which are NOT resettet.

Here is some piece of my trigger generation:

signal l_count : integer range 0 to 15;
signal l_trigger_watchdog : std_logic;

Trigger_watchdog <= l_trigger_watchdog;

--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_count <= 0;

if rising_edge(Clk_30) then
l_count <= l_count;

if l_count=15 then
l_count <= 0;
else
l_count <= l_count + 1;
end if;

end if;
end process;
--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_trigger_watchdog <= '0';

if rising_edge(Clk_30) then
l_trigger_watchdog <= l_trigger_watchdog;

if l_count=0 then
l_trigger_watchdog <= not l_trigger_watchdog;
end if;

end if;
end process;
--------------------------------------------
--------------------------------------------


Maybe someone has experienced such similar problems.

Thank you for your help.

Kind regards

André V.
 
ALuPin wrote:
Hi newsgroup people,

maybe someone can help me with regard to the following problem:

I am using an Altera Cyclone Device EP1C12F256C7.

When I program it via JTAG (I am not able to program it via Serial Configuration
Device yet) the PLL I instantiated in the MegaWizard does run if the PLL
does not have a reset input.

I have programmed a little design, some counters which are resetted.
It doesn't matter whether the counters are resetted or not I cannot see
anything going on at the debug pins of my FPGA.

So the question is what goes wrong.

I mean if it was a basic problem the PLL would not run.
If it was exclusevely an reset problem the counters WITHOUT reset would run
but they do not!

I have a watchdog which produces an asynchronous reset but then it does
not get the trigger signal out of the FPGA so that the watchdog resets
periodically. The trigger signal I generate in the FPGA is depedent on
the counters which are NOT resettet.

Here is some piece of my trigger generation:

signal l_count : integer range 0 to 15;
signal l_trigger_watchdog : std_logic;

Trigger_watchdog <= l_trigger_watchdog;

--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_count <= 0;

if rising_edge(Clk_30) then
l_count <= l_count;

if l_count=15 then
l_count <= 0;
else
l_count <= l_count + 1;
end if;

end if;
end process;
--------------------------------------------
--------------------------------------------
process(Clk_30)
begin
--if Reset='1' then
-- l_trigger_watchdog <= '0';

if rising_edge(Clk_30) then
l_trigger_watchdog <= l_trigger_watchdog;

if l_count=0 then
l_trigger_watchdog <= not l_trigger_watchdog;
end if;

end if;
end process;
--------------------------------------------
--------------------------------------------
Click to expand...
This code should work as far as I can tell. The statements where you
assign the count and trigger to themselves are not needed. I think you
may have included them for concern about generating latches if all cases
are not covered. But this only applies to combinatorial logic. You are
trying to infer sequential logic and so it is ok to have undefined
cases. The default is that the values are held if the conditions are
not defined (such as the else in the l_count=0 test).

I suggest that you bring out all the signals to pins, including the
clock. Then probe it all with a scope to see if anything is working.
Also make sure that the pins you want are really being used. If nothing
seems to work, check back to the synthesis equations to make sure your
design is not being optimized away.

--

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
 
This code should work as far as I can tell. The statements where you
assign the count and trigger to themselves are not needed. I think you
may have included them for concern about generating latches if all cases
are not covered. But this only applies to combinatorial logic. You are
trying to infer sequential logic and so it is ok to have undefined
cases. The default is that the values are held if the conditions are
not defined (such as the else in the l_count=0 test).

I suggest that you bring out all the signals to pins, including the
clock. Then probe it all with a scope to see if anything is working.
Also make sure that the pins you want are really being used. If nothing
seems to work, check back to the synthesis equations to make sure your
design is not being optimized away.
Click to expand...
Hi Rick,

thank you for your answer.

I have looked at the synthesis equations and the RTL viewer to check
the synthesis result. It seems everything to be OK.
The PLL is running that is PLL input is running and PLL output clock
is running as well. I have routet the PLL output clock (which feeds my
small test design) to a debug pin.
But the counter is not running. I have routet the bits of the 4bit counter
to debug pins but there is nothing happening on those pins.

My functional RESET is routet into the FPGA from a debug pin. It comes out
from a watchdog.

My counter is not resettet by that RESET. Could it be that the reset
signal destroys configuration? But on the other hand that would mean that
the PLL does not run. Or is a PLL handled separately?

I do not know where to search.

Maybe you have some idea.

p.s. I am using Altera QuartusII software and Cyclone device.

Kind regards
André
 
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