problems with asynhronous design

I had this interview questions regarding asynhronous design, and I was
not able to answer it. Question was regarding desing where one end of
the block was at x freq and other end of the block was at y freq.
So what are the problems associated with this design, and how can we
fix them.
Can you guys provide me few hints, pointers and suggestions
Thank you.

 

[Pinhas]

In this case some synchronization is required. There is a lot on the
web regarding clock domain synchronization.
If there is just one signal of control, you can just sample it twice.
When more signal are involved you may (for instance PCI to AHB
interface), you may need first to sample a control for starting a state
machine. The data would have to go via FIFO. There are examples on the
web of FIFO with gray pointers and different clock domains for read and
write.


ankitks@yahoo.com escreveu:

I had this interview questions regarding asynhronous design, and I was
not able to answer it. Question was regarding desing where one end of
the block was at x freq and other end of the block was at y freq.
So what are the problems associated with this design, and how can we
fix them.
Can you guys provide me few hints, pointers and suggestions
Thank you.