Problems with ADVance MS

[Johannes]

Hi,
I encountered some serious problems with this compiler. The following
file is compilable but not loadable!!!!

library disciplines;
use disciplines.electromagnetic_system.all;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;

LIBRARY IEEE;
USE ieee.numeric_std.ALL;


entity decimation_filter is
generic( K: integer:=4);

port ( clk,reset: in std_ulogic;
data_in : in signed (1 downto 0);
data_out : out signed (K downto 0);
external_clk: out std_ulogic);


end entity decimation_filter;


architecture structure of decimation_filter is

signal clkvec : std_ulogic_vector (1 to K):=(others=>'0');
signal sigvect1 : signed(1 downto 0);
signal sigvect2 : signed(2 downto 0);
signal sigvect3 : signed(3 downto 0);
signal sigvect4 : signed(4 downto 0);
signal test: std_logic_vector(4 downto 0);


begin

clkvec(1)<=clk;
sigvect1<=data_in;


filt_block1 : entity work.filter_block
generic map (N=>1)
port map (clk=>clkvec(1),
reset=>reset,
data_in=>sigvect1,
--data_out=>sigvect2, -- If I uncomment this line
data_out=>test(2 downto 0), --and comment this line
external_clk=>clkvec(2));

filt_block2 : entity work.filter_block
generic map (N=>2)
port map (clk=>clkvec(2),
reset=>reset,
--data_in=>sigvect2, --and uncomment this line
data_in=>test(2 downto 0), -- and comment this line it works
data_out=>sigvect3,
external_clk=>clkvec(3));

filt_block3 : entity work.filter_block
generic map (N=>3)
port map (clk=>clkvec(3),
reset=>reset,
data_in=>sigvect3,
data_out=>sigvect4,
external_clk=>clkvec(K));



data_out<=sigvect4;
external_clk<=clkvec(K);

end architecture;

To give you an overview over filter_block:




USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

entity filter_block is
generic( N: integer:=4);

port ( clk,reset: in std_ulogic;
data_in : in signed (N downto 0);
data_out : out signed ((N+1) downto 0);
external_clk: out std_ulogic
);

end entity filter_block;


architecture behavioral_ideal of filter_block is
signal filter_decimator : signed ((N+1) downto 0);
begin


fir_filter: entity work.fir
generic map (N => N)
port map ( clk =>clk,
reset => reset,
data_in=>data_in,
data_out=>filter_decimator);
decimator: entity work.decimator(behavioral_ideal)
generic map (N => N)
port map ( clk =>clk,
in_bitvector=>filter_decimator,
out_bitvector=>data_out,
external_clk=>external_clk);

end architecture;

If I change the test(2 downto 0) signal to sigvect2 it is compilable
AND loadable and simulateable.Does anybody have the slightest idea why
it behaves like that? I need this test(2 downto 0) stuff because i'd
like to do a generate.
Thank you for your help!

Johannes