A
Andy
Guest
Hi,
when I step into the matching phase of formality to compare my rtl
design with the corresponding netlist, the unmatched points summary
lists a lot of unmatched registers in my rtl design labelled as DFF0 or
DFF1 and this conclusion is logically correct. I think they are
recognized as unmatched points because the synthesis tool has made
optimization when it finds these registers resolved as constants and
simply saves a individual So can anyone tell me if I should do anything
with these kind of unmatched points before I go further into the verify
phase? Or if i ignore these mismatches, will they cause verification
failure?
when I step into the matching phase of formality to compare my rtl
design with the corresponding netlist, the unmatched points summary
lists a lot of unmatched registers in my rtl design labelled as DFF0 or
DFF1 and this conclusion is logically correct. I think they are
recognized as unmatched points because the synthesis tool has made
optimization when it finds these registers resolved as constants and
simply saves a individual So can anyone tell me if I should do anything
with these kind of unmatched points before I go further into the verify
phase? Or if i ignore these mismatches, will they cause verification
failure?