Problem :(

W

Wojtek

Guest
Hi, I have a problem:

entity Data_Bus_Buffer is

port(
clk : in std_logic;
P_I_Load : in std_logic;
P_I_Store : in std_logic;
P_IO_D0 : inout std_logic;
P_IO_D1 : inout std_logic;
P_IO_D2 : inout std_logic;
P_IO_D3 : inout std_logic;

P_IO_Bus : inout std_logic_vector(3 downto 0)

);

end Data_Bus_Buffer;

architecture Behavioral of Data_Bus_Buffer is



begin

zegar: process(clk,P_I_Load,P_I_Store)


begin

if (clk'event and clk = '1') then


if (P_I_Load = '1' and P_I_Store = '0') then

P_IO_Bus(3) <= P_IO_D3;
P_IO_Bus(2) <= P_IO_D2;
P_IO_Bus(1) <= P_IO_D1;
P_IO_Bus(0) <= P_IO_D0;


elsif (P_I_Load = '0' and P_I_Store = '1') then



P_IO_D3 <= P_IO_Bus(3);
P_IO_D2 <= P_IO_Bus(2);
P_IO_D1 <= P_IO_Bus(1);
P_IO_D0 <= P_IO_Bus(0);



else

P_IO_Bus <= "ZZZZ";
P_IO_D0 <= 'Z';
P_IO_D1 <= 'Z';
P_IO_D2 <= 'Z';
P_IO_D3 <= 'Z';

end if;
end if;

end process zegar;
end;




When i am simulating I can not initalize in testbench ports P_IO_DX before
P_I_Load = '0';

MAybe I should use only ports of type 'in' or 'out', and not inout ??
 
The 'zegar' process will be actively driving the P_IO_Dx inout signals
until AFTER the rising edge of clock that occurs when P_I_LOAD and
P_I_STORE are both either '0' or both '1'. You probably wanted
something more along the lines of what is pasted below.

zegar: process(clk,P_I_Load,P_I_Store)
begin
if (clk'event and clk = '1') then
if (P_I_Load = '1' and P_I_Store = '0') then
P_IO_Bus(3) <= P_IO_D3;
P_IO_Bus(2) <= P_IO_D2;
P_IO_Bus(1) <= P_IO_D1;
P_IO_Bus(0) <= P_IO_D0;
end if;
end if;
end process zegar;

zegar2 : process(P_I_LOAD, P_I_STORE, P_IO_BUS)
begin
if (P_I_Load = '0' and P_I_Store = '1') then
P_IO_D3 <= P_IO_Bus(3);
P_IO_D2 <= P_IO_Bus(2);
P_IO_D1 <= P_IO_Bus(1);
P_IO_D0 <= P_IO_Bus(0);
else
P_IO_Bus <= "ZZZZ";
P_IO_D0 <= 'Z';
P_IO_D1 <= 'Z';
P_IO_D2 <= 'Z';
P_IO_D3 <= 'Z';
end if;
end process zegar2;

KJ
 
zegar: process(clk,P_I_Load,P_I_Store)
Click to expand...

is it correct? Clk, P_I_Load, P_I_Store in this line? If yes, why not
P_IO_Dx ??

Thank you
Wojtek
 
Oops. No, it should just be

zegar: process(clk)

Nothing actually happens inside the 'zegar' process unless 'clk'
changes. When any of the other signals changes (without a coincidental
change in 'clk' as well) nothing happens inside the 'zegar' process
since the outermost loop looks for clk'event and clk = '1'.

KJ
 
Uzytkownik "KJ" <Kevin.Jennings@Unisys.com> napisal w wiadomosci
news:1146511673.245557.326280@u72g2000cwu.googlegroups.com...
Oops. No, it should just be

zegar: process(clk)

Nothing actually happens inside the 'zegar' process unless 'clk'
changes. When any of the other signals changes (without a coincidental
change in 'clk' as well) nothing happens inside the 'zegar' process
since the outermost loop looks for clk'event and clk = '1'.
Click to expand...
:)

zegar2 : process(P_I_LOAD, P_I_STORE, P_IO_BUS)

and that is correct?

thank you so much :)

Wojtek
 
Uzytkownik "KJ" <Kevin.Jennings@Unisys.com> napisal w wiadomosci
news:1146503650.957752.147060@e56g2000cwe.googlegroups.com...
The 'zegar' process will be actively driving the P_IO_Dx inout signals
until AFTER the rising edge of clock that occurs when P_I_LOAD and
P_I_STORE are both either '0' or both '1'. You probably wanted
something more along the lines of what is pasted below.
Click to expand...

I would like to make data_buffer.


RAM <=> data_buffer <=> bus

bidirect lines are too dificult for me :(


Wojtek
 
I'd split each inout into a separate in and out if possible. Probably
best to avoid inouts whenever possible.



---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps
 
Let's see if I understand what you want to achieve:
As far as I understand you want to connect two "inout" busses and you
want to put a register stage between them.

Try that ( I changed the names somewhat to save time):

entity Data_Bus_Buffer is
port (
iClk : in STD_LOGIC;
iLoad : in STD_LOGIC; -- When 1 drive ioBusB to ioBusA
iStore: in STD_LOGIC; -- When 1 drive ioBusA to ioBusB
ioBusA : inout STD_LOGIC_VECTOR(3 downto 0);
ioBusB : inout STD_LOGIC_VECTOR(3 downto 0)
);
end Data_Bus_Buffer;

architecture whatever of Data_Bus_Buffer is

signal rLoad, rStore : STD_LOGIC;
signal rD : STD_LOGIC_VECTOR(3 downto 0);
begin
ioBusA <= rD when rLoad='1' and rStore='0' else (others => 'Z');
ioBusB <= rD when rLoad='0' and rStore='1' else (others => 'Z');
process(iClk) -- (No other signals necessary)
begin
if iClk'event and iClk='1' then
rLoad <= iLoad;
rStore <= iStore;
if iLoad='1' and iStore='0' then
rD<=ioBusB;
end if;
if iLoad='0' and iStore='1' then
rD<=ioBusA;
end if;
end if;
end process;
end whatever;


Sorry if there are type mistakes in that code, I just hacked it right
here.
Tell me if this is what you wanted.

so long
lundril
 
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