Problem writing output result to text file

[Lily]

Hello,

I'd like to write the output of my testbench to a text file.
Unfortunately now, the stimulus.dat (my output text file) is just
rubbish. The results are perfect when i checked using waveform. I
suspect there is something wrong with the timing in my program, but
dont have any clue how to solve it. are they any suggestions/advice to
solve this ? thanks in advance. below is my testbench code :-

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_ARITH.ALL;
library std;



entity alu_testbench is
end alu_testbench;

architecture test_alu of alu_testbench is
component alu_structure
generic(
OPERAND_WIDTH : integer := 8);
Port (
-- The input/ouput interface of the module
S : in std_logic_vector(3 downto 0);
A : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
B : in std_logic_vector(OPERAND_WIDTH-1 downto 0);
Y : out std_logic_vector(OPERAND_WIDTH-1 downto 0);
CI : out std_logic;
C, V, Z : out std_logic;
clk : in std_logic;
reset : in std_logic
);
end component;



-- declare math opcode constants
constant ADD : std_logic_vector(3 downto 0) := "0000";
constant SUB : std_logic_vector(3 downto 0) := "0010";
constant INC : std_logic_vector(3 downto 0) := "0001";
constant CMP : std_logic_vector(3 downto 0) := "0011";

-- declare logical opcode constants
constant opAND : std_logic_vector(3 downto 0) := "1100";
constant opOR : std_logic_vector(3 downto 0) := "1101";
constant opXOR : std_logic_vector(3 downto 0) := "1110";
constant opCPL : std_logic_vector(3 downto 0) := "1111";

constant OPERAND_WIDTH : integer := 8;
constant clk_period : time := 10 ns;

signal clock : std_logic;
signal rst : std_logic;
signal S : std_logic_vector(3 downto 0);
signal A : std_logic_vector(OPERAND_WIDTH-1 downto 0);
signal B : std_logic_vector(OPERAND_WIDTH-1 downto 0);
signal alu_result : std_logic_vector(OPERAND_WIDTH-1 downto 0);

signal CI : std_logic;
signal C, V, Z : std_logic;
signal done : std_logic;


for t1 : alu_structure use entity work.alu_structure(alu_arch);


begin -- behavior
t1 : alu_structure


port map (
S => S,
A => A,
B => B,
Y => alu_result,
CI => CI,
C => C,
V => V,
clk => clock,
reset => rst,
Z => Z

);

-- reset process
reset : process
begin
rst <='0','1' after 100 ns;
wait for 1 ms;
end process reset;




-- clock process

clk : process
begin
clock <= '0', '1' after 50 ns;
wait for 100 ns;
end process clk;



-- prinstatus
prinstatus : process (clock, rst)

file infile : text is in
"/elhome/elhh2/ALU_MODEL/alu_example/command.dat";
file outfile : text is out
"/elhome/elhh2/ALU_MODEL/alu_example/stimulus.dat";
variable aluinput : std_logic_vector(19 downto 0);
variable aluoutput : std_logic_vector(7 downto 0);
variable buff : line;

begin -- process
if rst = '0' then
A <= "00000000";
B <= "00000000";
alu_result <= "00000000";

elsif clock'event and clock = '1' then
if not (endfile(infile)) then
readline(infile,buff);
read(buff,aluinput);

B <= aluinput(7 downto 0);
A <= aluinput(15 downto 8);
S <= aluinput(19 downto 16);


elsif rising_edge(clock) then
aluoutput(7 downto 0) := alu_result;

write(buff,aluoutput);
writeline(outfile,buff);


end if;
end if;
end process prinstatus;

end test_alu;

 

[Amontec Team]

Lily wrote:

Hello,

I'd like to write the output of my testbench to a text file.
Unfortunately now, the stimulus.dat (my output text file) is just
rubbish. The results are perfect when i checked using waveform. I
suspect there is something wrong with the timing in my program, but
dont have any clue how to solve it. are they any suggestions/advice to
solve this ? thanks in advance. below is my testbench code :-

library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use IEEE.STD_LOGIC_ARITH.ALL;
library std;

-- ...

Don't use both ieee.numeric_std.all and IEEE.STD_LOGIC_ARITH.ALL.

Please remove the IEEE.STD_LOGIC_ARITH.ALL.

And run again !

Laurent Gauch
www.amontec.com