problem with xc3s400 place and rout section

[nba83]

hi
i have a custom designed board with xilinx spartan 3( xc3s400 ) with tw
ethernet phy layer (RTL8201) for a two port switch. I have a ring networ
of 10 of this board on the chain. i transmit data from the first board an
count the number of packets from the last ethernet port of the tenth boar
to test the integrity of switch and the hdl code.
the code in some synthesis work without error but when i add another piec
of code for example a counter which is unrelated to the other logics and r
synthesis the code the previous parts of my code work with error.
i guess it is due to place and route section and timing constranits o
ethernet phy layer. this phy layer has 2 independ transmit and receive cl
and due to ease of pcb routing i connected these clk signals to normal pin
not the global clk pins and now i think the timing constraints are disable
since i used this contraint on the pin NET "RTL_RXCLK
CLOCK_DEDICATED_ROUTE = "FALSE";
in timing reports it is said that all timing constraints are met but ther
is warning saying “The use of
this override is highly discouraged as it may lead to very poor timin
results” . what is the problem and
how can i fixed the problem ?i cannot change the pcb because of the pric
and time is it possible to check and apply timing constraints in fpg
editor?
Tnx in advanced for any helpful comment
Neda Baheri


---------------------------------------
Posted through http://www.FPGARelated.com

 

[GaborSzakacs]

nba83 wrote:

hi
i have a custom designed board with xilinx spartan 3( xc3s400 ) with two
ethernet phy layer (RTL8201) for a two port switch. I have a ring network
of 10 of this board on the chain. i transmit data from the first board and
count the number of packets from the last ethernet port of the tenth board
to test the integrity of switch and the hdl code.
the code in some synthesis work without error but when i add another piece
of code for example a counter which is unrelated to the other logics and re
synthesis the code the previous parts of my code work with error.
i guess it is due to place and route section and timing constranits of
ethernet phy layer. this phy layer has 2 independ transmit and receive clk
and due to ease of pcb routing i connected these clk signals to normal pins
not the global clk pins and now i think the timing constraints are disabled
since i used this contraint on the pin NET "RTL_RXCLK"
CLOCK_DEDICATED_ROUTE = "FALSE";
in timing reports it is said that all timing constraints are met but there
is warning saying “The use of
this override is highly discouraged as it may lead to very poor timing
results” . what is the problem and
how can i fixed the problem ?i cannot change the pcb because of the price
and time is it possible to check and apply timing constraints in fpga
editor?
Tnx in advanced for any helpful comment
Neda Baheri


---------------------------------------
Posted through http://www.FPGARelated.com

The CLOCK_DEDICATED_ROUTE constraint will not disable timing analysis.
It is only a routing directive. If you have timing constraints
that cover the period, clock to output, setup and hold for this
clock, then you should still be able to see if there are timing
issues after static timing analysis.

I generally recommend generating a verbose timing report with
"report unconstrained paths" set to a large number like 100.
This might show areas that need additional constraints.

On the other hand, there is still the possibility that this
design has errors in clock crossing logic or asynchronous
signal synchronization. That sort of problem very often
comes and goes with a new build due to changes in placement,
and therefore changes in relative routing delays of the
poorly handled signals.

--
Gabor

 

[nba83]

nba83 wrote:
hi
i have a custom designed board with xilinx spartan 3( xc3s400 ) wit
two
ethernet phy layer (RTL8201) for a two port switch. I have a rin
network
of 10 of this board on the chain. i transmit data from the first boar
and
count the number of packets from the last ethernet port of the tent
board
to test the integrity of switch and the hdl code.
the code in some synthesis work without error but when i add anothe
piece
of code for example a counter which is unrelated to the other logics an
re
synthesis the code the previous parts of my code work with error.
i guess it is due to place and route section and timing constranits of
ethernet phy layer. this phy layer has 2 independ transmit and receiv
clk
and due to ease of pcb routing i connected these clk signals to norma
pins
not the global clk pins and now i think the timing constraints ar
disabled
since i used this contraint on the pin NET "RTL_RXCLK"
CLOCK_DEDICATED_ROUTE = "FALSE";
in timing reports it is said that all timing constraints are met bu
there
is warning saying “The use of
this override is highly discouraged as it may lead to very poor timing
results” . what is the problem and
how can i fixed the problem ?i cannot change the pcb because of th
price
and time is it possible to check and apply timing constraints i
fpga
editor?
Tnx in advanced for any helpful comment
Neda Baheri


---------------------------------------
Posted through http://www.FPGARelated.com

The CLOCK_DEDICATED_ROUTE constraint will not disable timing analysis.
It is only a routing directive. If you have timing constraints
that cover the period, clock to output, setup and hold for this
clock, then you should still be able to see if there are timing
issues after static timing analysis.

I generally recommend generating a verbose timing report with
"report unconstrained paths" set to a large number like 100.
This might show areas that need additional constraints.

On the other hand, there is still the possibility that this
design has errors in clock crossing logic or asynchronous
signal synchronization. That sort of problem very often
comes and goes with a new build due to changes in placement,
and therefore changes in relative routing delays of the
poorly handled signals.

--
Gabor

Tnx for your helpful comment. I have 6 clock signals: 2 tx_clk(25MHz),
rx_clk(25MHz) for 2 Phy layers, 1 for adc sampling(1MHz) , 1 for spi(1MHz
communication. I only have period constraint for 25MHz clk signal. I don'
have any idea how to set clock to output, setup and hold constraints fo
these clocks. and for 1MHz clocks there is no time constraint (since thes
clocks are so slow to set any constraints).
how should I know from verbose timing report that which areas nee
additional constraints? and how should I apply the changes to my design?
I hardly think there must be cross clocking domain issues, I have buffer
to receive data from RX clock and transmit from TX clock.
Tnx in advanced for any helpful comment
Neda Baheri

---------------------------------------
Posted through http://www.FPGARelated.com