Problem with Verilog testbench in ModelSim

[czeczek]

Hi All,

I've created following test bench for testing some fsm module. I
created two initial processes, one for initialization of clock and
reset and other one for injecting input pattern at the negative clock
edge to the tested module. There are two more processes here, one
"always" generating clock and other one displaying data at each
positive clock edge.
Problem is that, if I simulate this tb it always stops displaying
results not at the last injected value but previous one (bit =0 in
in_data).
Performing simulation for few more tens of nanoseconds it finally
displays last injected value and result which comes from tested module.
How can I change this test bench to see all injected values during
simulation without adding constant delays before $stop. ? (Below is
also output from tb, interested time is from 13 to 33)

I thought it should behave as executed in parallel but it's not.

Thanks
Marcin

--------cut here --------
module tb;

reg in,clk,reset;
wire [2:0] out;

fsmBehav
fsmModule (.out(out), .in(in), .clk(clk), .reset(reset));

integer idx;
reg [10:0] in_data = 11'b11010001100;

initial
begin
clk = 0; reset=0;
#10 reset=1;
end

always
begin
#1 clk = ~clk;
end

always
begin
wait(reset)
@(posedge clk)
$display($time,,,,"In=%b, Out=%b", in, out);
end

initial
begin
wait(reset)
for (idx=10; idx>=0; idx=idx-1) begin
@(negedge clk) in <= in_data[idx];
end
$stop;
end
endmodule
--------cut here --------
--------- output -----------
run -all
# 11 In=x, Out=z11
# 13 In=1, Out=z11
# 15 In=1, Out=101
# 17 In=0, Out=010
# 19 In=1, Out=z11
# 21 In=0, Out=z11
# 23 In=0, Out=101
# 25 In=0, Out=101
# 27 In=1, Out=101
# 29 In=1, Out=010
# 31 In=0, Out=z11
Additional run !
run 10ns
# 33 In=0, Out=101

 

[Mark McDougall]

czeczek wrote:

always
begin
wait(reset)
@(posedge clk)
$display($time,,,,"In=%b, Out=%b", in, out);
end

initial
begin
wait(reset)
for (idx=10; idx>=0; idx=idx-1) begin
@(negedge clk) in <= in_data[idx];
end
$stop;
end

You're telling it to stop immediately after a negedge, but only printing
on posedge, so after the *last* assignment the simulation is ending
before the print is executed on the next posedge.

There are several ways to 'fix' the problem, which I'm sure you're quite
capable of...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

 

[czeczek]

Mark,
Thanks for that point. I have no idea why I didn't notice it ? Probably
because of long day
Adding @(negedge clk) before $stop is a resolution.

Marcin

Mark McDougall wrote:

czeczek wrote:

always
begin
wait(reset)
@(posedge clk)
$display($time,,,,"In=%b, Out=%b", in, out);
end

initial
begin
wait(reset)
for (idx=10; idx>=0; idx=idx-1) begin
@(negedge clk) in <= in_data[idx];
end
$stop;
end

You're telling it to stop immediately after a negedge, but only printing
on posedge, so after the *last* assignment the simulation is ending
before the print is executed on the next posedge.

There are several ways to 'fix' the problem, which I'm sure you're quite
capable of...

Regards,

--
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266