problem with unsigned

[Apo]

Hi All, I have a problem.

I can't understand why, with my modelsim 5,7c , in some circumstaces I can
compile the script below but when I'm exporting from EDK project to model
sim for a behaviourl test of an Ip core it return this error:

# ** Error:
C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
identifer unsigned is not visible. Making two objects with the name
"unsigned" directly visible via use clauses results in a conflict, neither
object is made directly visible.(LRM Section 10.4).

Definition include from:

ieee.std_logic_arith.unsigned

ieee.numeric_std.unsigned



The script is:

TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8)

it is nested in:

return word(

TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &

TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &

TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &

TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)

);

where Word is

SUBTYPE word IS std_logic_vector(31 DOWNTO 0);



Thank you

Alain

 

[Mike Treseler]

Apo wrote:

I can't understand why, with my modelsim 5,7c , in some circumstaces I
can compile the script below but when I'm exporting from EDK project to
model sim for a behaviourl test of an Ip core it return this error:

# ** Error:
C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
identifer unsigned is not visible. Making two objects with the name
"unsigned" directly visible via use clauses results in a conflict, neither
object is made directly visible.(LRM Section 10.4).

Definition include from:
ieee.std_logic_arith.unsigned
ieee.numeric_std.unsigned

what happens if you do this

use ieee.numeric_std.all
-- use ieee.std_logic_arith.unsigned

?

return word(
TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)
);

where Word is
SUBTYPE word IS std_logic_vector(31 DOWNTO 0);

I will assume that you are not really trying to return a subtype.

-- Mike Treseler

 

[Apo]

"Mike Treseler" <mike_treseler@comcast.net> ha scritto nel messaggio
news:fLidnYUryOq9MtDcRVn-vQ@comcast.com...

Apo wrote:


I can't understand why, with my modelsim 5,7c , in some circumstaces I
can compile the script below but when I'm exporting from EDK project to
model sim for a behaviourl test of an Ip core it return this error:

# ** Error:

C:/ppp/AES_EDK_KVERBAK/pcores/kver_v1_00_a/hdl/vhdl/kver_module.vhd(176):
identifer unsigned is not visible. Making two objects with the name
"unsigned" directly visible via use clauses results in a conflict,
neither
object is made directly visible.(LRM Section 10.4).

Definition include from:
ieee.std_logic_arith.unsigned
ieee.numeric_std.unsigned

what happens if you do this

use ieee.numeric_std.all
-- use ieee.std_logic_arith.unsigned

?

return word(
TO_UNSIGNED(SBOX(To_INTEGER(unsigned(input(31 downto 24)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(23 downto 16)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input(15 downto 8)))), 8) &
TO_UNSIGNED(SBOX(TO_INTEGER(unsigned(input( 7 downto 0)))), 8)
);

where Word is
SUBTYPE word IS std_logic_vector(31 DOWNTO 0);

I will assume that you are not really trying to return a subtype.

What do you mean? how can convert a integer to a std_logic_vector or
something similar?

ah.. with your correction it seems work

-- Mike Treseler

Thanks for help

Alain