Problem with this sawtooth generator...

P

Paul Burridge

Guest
Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?

Thanks,

p.
--

My opinion is worth what you've paid for it.
 
"Paul Burridge" <pb@osiris1.notthisbit.co.uk> schreef in bericht
news:0jq000pv8o6m1f9b359sv4n48ua3i7vsai@4ax.com...
Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?
Click to expand...
sawtooth or triangular?

--
Thanks, Frank.
(remove 'x' and 'invalid' when replying by email)
 
Paul Burridge wrote:
Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?
Click to expand...
The start up problem is an artifact of the perfection of components in
the simulation. The first opamp is supposed to saturate with any tiny
input voltage to either full positive or negative output swing,
causing the second opamp to immediately begin integrating up or down
at the full ramp speed. But the math of the simulation starts the cap
at exactly zero volts across it, and both opamps have exactly zero
offset voltage, so there is exactly zero volts across both opamp
inputs at the start of the simulation, so even with the positive
feedback around the first stage, there is exactly zero to amplify,
till accumulation of round off errors at the 9th or so digit finally
creates enough voltage to get the first stage latched up. The chance
of this happening in real life is very slim.

Try this to prove me wrong. Build a second reference voltage by
putting a third resistor between the first two (R2 and 3) of say, 470
ohms. Use the top end for the - input of first amp, and the bottom
for the + input of the second (or vice versa). This will produce a
small voltage for the integrator even at the start, getting things
rolling much earlier.

Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.

--
John Popelish
 
On Sat, 10 Jan 2004 21:16:02 +0000, Paul Burridge <pb@osiris1.notthisbit.co.uk>
wroth:

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?

C1 has zero volts across it when the circuit is first turned on. After
Click to expand...
the first cycle, the voltage across C1 changes between two values set by the
comparator stage and niether one is zero. That's why the first cycle is so
long.

555 circuits suffer from this also. Before I looked at your .gif I had
a bet with myself that you were using a 555.

Redesign the circuit so that the cap charges from zero to some set point
and back again.

Jim
 
Paul Burridge wrote:
Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?

Thanks,

p.
Click to expand...
You bet!
Add a flip-flop that powers up in a known state.
Use the first cycle of the output to clock the flop into it's other
state. Run the output of the flop to a spdt relay that opens the
path to the drive resistor and stuffs in a known high current of the
proper direction to make the output go to the right state to clock
the flip-flop. Don't forget to simulate the contact bounce.

I would have suggested using a microcontroller for the startup sequence,
but that would be hard to simulate in spice.

When you get that working, we can talk about some of the other problems
with the implementation. Are we having fun yet? Well, I sure am...

As always, design first, simulate second.
mike

--
Return address is VALID.
Bunch of stuff For Sale and Wanted at the link below.
Toshiba & Compaq LiIon Batteries, Test Equipment
Honda CB-125S $800 in PDX
TEK Sampling Sweep Plugin and RM564
Tek 2465 $800, ham radio, 30pS pulser
Tektronix Concept Books, spot welding head...
http://www.geocities.com/SiliconValley/Monitor/4710/
 
On Sat, 10 Jan 2004 21:16:02 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?

Thanks,

p.
Click to expand...
Paul, I thought we relegated you to S.E.BASICS ?:)

Where did you dig up that schematic?

Ever wondered how an electrolytic capacitor acts when reverse-biased?

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
John Popelish wrote:

The start up problem is an artifact of the perfection of components in
the simulation. The first opamp is supposed to saturate with any tiny
input voltage to either full positive or negative output swing,
causing the second opamp to immediately begin integrating up or down
at the full ramp speed. But the math of the simulation starts the cap
at exactly zero volts across it, and both opamps have exactly zero
offset voltage, so there is exactly zero volts across both opamp
inputs at the start of the simulation, so even with the positive
feedback around the first stage, there is exactly zero to amplify,
till accumulation of round off errors at the 9th or so digit finally
creates enough voltage to get the first stage latched up. The chance
of this happening in real life is very slim.

Try this to prove me wrong. Build a second reference voltage by
putting a third resistor between the first two (R2 and 3) of say, 470
ohms. Use the top end for the - input of first amp, and the bottom
for the + input of the second (or vice versa). This will produce a
small voltage for the integrator even at the start, getting things
rolling much earlier.

Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.
Click to expand...
Don't forget to add that the circuit does not generate a sawtooth even
when it does finally start:)
 
James Meyer wrote:

C1 has zero volts across it when the circuit is first turned on. After
the first cycle, the voltage across C1 changes between two values set by the
comparator stage and niether one is zero. That's why the first cycle is so
long.
Click to expand...
Actually this makes the first integrator cycle short. The steady state
operation is for the capacitor to charge through a 10V excursion, the
first cycle requires only 5V to reach a switchpoint.
 
On Sat, 10 Jan 2004 16:22:36 -0700, Jim Thompson
<thegreatone@example.com> wrote:

Paul, I thought we relegated you to S.E.BASICS
Click to expand...
I thought you'd relegated me to your killfile! Obviously my
irrisistable magnetic popularity has worked its magic again. :)

Where did you dig up that schematic?
Click to expand...
A search of the web. Yes, it *is* actually a triangle generator as
someone else has pointed out.

Ever wondered how an electrolytic capacitor acts when reverse-biased?
Click to expand...
Well, the original design called for a 22nF but worked at a much
higher cycle rate. I found that by changing some of the values
(including that cap) that I could get the cycle rate *much* lower.
Unfortunately somewhere along the way I forgot I wasn't going to be
able to find a 220uF unpolarised cap. D'oh! Spice should have warned
me. :-(
--

My opinion is worth what you've paid for it.
 
On Sat, 10 Jan 2004 22:43:28 GMT, John Popelish <jpopelish@rica.net>
wrote:

[snipped but noted]

Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.
Click to expand...
I guess I'll have to use a bunch of smaller value unpolarised caps in
parallel. Sigh...

--

My opinion is worth what you've paid for it.
 
On Sun, 11 Jan 2004 00:21:43 +0000, Paul Burridge
<pb@osiris1.notthisbit.co.uk> wrote:

On Sat, 10 Jan 2004 16:22:36 -0700, Jim Thompson
thegreatone@example.com> wrote:

Paul, I thought we relegated you to S.E.BASICS

I thought you'd relegated me to your killfile! Obviously my
irrisistable magnetic popularity has worked its magic again. :)

[snip]
Click to expand...

No. Someone else replied to you and I saw the reply. I couldn't
resist taking yet another poke at you ;-)

...Jim Thompson
--
| James E.Thompson, P.E. | mens |
| Analog Innovations, Inc. | et |
| Analog/Mixed-Signal ASIC's and Discrete Systems | manus |
| Phoenix, Arizona Voice:(480)460-2350 | |
| E-mail Address at Website Fax:(480)460-2142 | Brass Rat |
| http://www.analog-innovations.com | 1962 |

I love to cook with wine. Sometimes I even put it in the food.
 
Paul Burridge wrote:
Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?
Click to expand...
Why not generate it digitally? All you need is a suitable MCU and DAC.
The 'steps' in the waveform probably won't matter.


Leon
--
Leon Heller, G1HSM
Email: aqzf13@dsl.pipex.com
My low-cost Philips LPC210x ARM development system:
http://www.geocities.com/leon_heller/lpc2104.html
 
In article <0jq000pv8o6m1f9b359sv4n48ua3i7vsai@4ax.com>,
Paul Burridge <pb@osiris1.notthisbit.co.uk> wrote:

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case
220uF). Problem is, the output doesn't start to do anything until
over 7 minutes after switch-on! Is there any way of reducing this
to a much shorter delay without increasing the output frequency?
Click to expand...
At switch-on, (with 0v on the cap), the first ramp should
start from Vcc/2, then move to one of the outer switching
points, and that should only take 1/2 the normal ramp time.

Looks like John Popelish has nailed it exactly, as an
artifact of simulation, and a small unbalance in the ratio
of R2 to R3 should send the (non-)problem away.

--
Tony Williams.
 
On Sat, 10 Jan 2004 17:23:03 -0700, Jim Thompson
<thegreatone@example.com> wrote:

No. Someone else replied to you and I saw the reply. I couldn't
resist taking yet another poke at you ;-)
Click to expand...
There you go, you see: missing out on all this fun. Fish in a barrel;
shooting ducks. :)
--

My opinion is worth what you've paid for it.
 
On Sun, 11 Jan 2004 03:48:20 +0000, Leon Heller <aqzf13@dsl.pipex.com>
wrote:

Paul Burridge wrote:

Gentlemen,

May I refer you to the following page where you will find the circuit
concerned:

http://www.burridge8333.fsbusiness.co.uk/sawtooth.gif

I need a very slow cycle rate of around 1 per minute, which
necessitates a reasonably large value capacitor (in this case 220uF).
Problem is, the output doesn't start to do anything until over 7
minutes after switch-on! Is there any way of reducing this to a much
shorter delay without increasing the output frequency?

Why not generate it digitally? All you need is a suitable MCU and DAC.
The 'steps' in the waveform probably won't matter.
Click to expand...
Yes, even relatively large steps wouldn't matter in this case, but I'm
hoping for a solution with the existing circuit for the sake of
expediency. I've had some useful feedback and will try a few things...
--

My opinion is worth what you've paid for it.
 
On Sat, 10 Jan 2004 22:43:28 GMT, John Popelish <jpopelish@rica.net>
wrote:

Try this to prove me wrong. Build a second reference voltage by
putting a third resistor between the first two (R2 and 3) of say, 470
ohms. Use the top end for the - input of first amp, and the bottom
for the + input of the second (or vice versa). This will produce a
small voltage for the integrator even at the start, getting things
rolling much earlier.
Click to expand...
I'll certainly give it a bash.

Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.
Click to expand...
I'll parallel some smaller non-polarised ones up in lieu. What's the
largest-value non-polarised cap commonly available?
--

My opinion is worth what you've paid for it.
 
Paul Burridge wrote:

On Sat, 10 Jan 2004 22:43:28 GMT, John Popelish <jpopelish@rica.net
wrote:

[snipped but noted]


Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.


I guess I'll have to use a bunch of smaller value unpolarised caps in
parallel. Sigh...

Nichicon's ES series of nonpolarized caps includes a 220uF value. They
Click to expand...
describe leakage current this way:

"Leakage Current: After 1 minute's application of rated voltage, leakage
current is not more than 0.03CV or 3 (ľA), whichever is greater."

You can start here:

http://www.nichicon.com/english/seihin/alm_mini/list_f.htm

--
Mike "Rocket J Squirrel" Elliott
71 VW Type 2 -- the Wonderbus (AKA the Saunabus in summer)
 
On Sun, 11 Jan 2004 16:25:00 GMT, the renowned "Mike Rocket J.
Squirrel Elliott"
<j.michael.elliottAT@REMOVETHEOBVIOUSadelphiaDOT.net> wrote:

Paul Burridge wrote:

On Sat, 10 Jan 2004 22:43:28 GMT, John Popelish <jpopelish@rica.net
wrote:

[snipped but noted]


Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.


I guess I'll have to use a bunch of smaller value unpolarised caps in
parallel. Sigh...

Nichicon's ES series of nonpolarized caps includes a 220uF value. They
describe leakage current this way:

"Leakage Current: After 1 minute's application of rated voltage, leakage
current is not more than 0.03CV or 3 (ľA), whichever is greater."

You can start here:

http://www.nichicon.com/english/seihin/alm_mini/list_f.htm
Click to expand...

It would be a lot more sensible to redesign the circuit so the
capacitor is only biased in one direction. Low-leakage caps are almost
10x better.

Best regards,
Spehro Pefhany
--
"it's the network..." "The Journey is the reward"
speff@interlog.com Info for manufacturers: http://www.trexon.com
Embedded software/hardware/analog Info for designers: http://www.speff.com
 
On Sun, 11 Jan 2004 13:47:16 +0000, Paul Burridge <pb@osiris1.notthisbit.co.uk>
wroth:

Why not generate it digitally? All you need is a suitable MCU and DAC.
The 'steps' in the waveform probably won't matter.

Yes, even relatively large steps wouldn't matter in this case, but I'm
hoping for a solution with the existing circuit for the sake of
expediency. I've had some useful feedback and will try a few things...
Click to expand...
Did you really need a sawtooth wave? If so, I think I can come up with
a very simple, slow as you want, circuit.

Jim
 
Paul Burridge wrote:
On Sat, 10 Jan 2004 22:43:28 GMT, John Popelish <jpopelish@rica.net
wrote:
(snip)
Then you have to worry about where you are going to find a low
leakage, non polarized 220 uf cap.

I'll parallel some smaller non-polarised ones up in lieu. What's the
largest-value non-polarised cap commonly available?
Click to expand...
10 uf is about as big as I have seen that are easily mounted by their
leads. Digikey has the Panasonic E series available up to 10 uf. And
you can raise the value of the input resistor to the second opamp
quite a bit as long as you use a low bias current opamp. Something up
to 10 meg should be no problem. This is a lot cheaper then
accumulating 220 uf. You can also reduce the voltage swing of the
first opamp by several different means, and reduce the current through
the second stage input resistor to slow the charging.

--
John Popelish
 
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