problem with the GTX wrapper in questa

R

rahulkhikher

Guest
Hi,


Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04.


I am trying to simulate GTX wrapper (generated from xilinx coregen) i
questasim. Steps followed by me :

1.Compliled the all xilinx library using "compxlibgui" in questasim.

2.Then copy the modelsim.in into the working directory of project.

3.launched the vsim with the "-L" switch for libraries and with -novopt



I am facing the following error while simulation:

.....

# Refreshin
/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo
# Refreshin
/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo

Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1.
# Time: 0 fs Iteration: 0 Instance:
/LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i
File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd
Line: 54
# FATAL ERROR while loading design
# Error loading design
Error loading design



I am able to simulate the same project in the ISIM.


Please replay me the solution of this issue.



Thanks,

Rahul




---------------------------------------
Posted through http://www.FPGARelated.com
 
Am Dienstag, 11. Juni 2013 12:39:32 UTC+2 schrieb rahulkhikher:
Hi,





Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04.





I am trying to simulate GTX wrapper (generated from xilinx coregen) in

questasim. Steps followed by me :



1.Compliled the all xilinx library using "compxlibgui" in questasim.



2.Then copy the modelsim.in into the working directory of project.



3.launched the vsim with the "-L" switch for libraries and with -novopt







I am facing the following error while simulation:



....



# Refreshing

/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo

# Refreshing

/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo



Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1.

# Time: 0 fs Iteration: 0 Instance:

/LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i

File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd

Line: 54

# FATAL ERROR while loading design

# Error loading design

Error loading design







I am able to simulate the same project in the ISIM.





Please replay me the solution of this issue.







Thanks,



Rahul









---------------------------------------

Posted through http://www.FPGARelated.com
Click to expand...
Hi Rahul,
do as the error message says:
Check the file GTXE1.vhd (or the instantiating TB) for a generic AC_CAP_DIS.
The range of that generic is 0 to 1, and the actual setting is reported to be 1095521093.
Maybe some number gets misinterpreted for some reason.
(Are you just using VHDL or are there other languages involved (verilog, Systemverilog)?

If you don't find anything reasonable, it might also be a simple bug.

Have a nice simulation
Eilert
 
[snipped]

Somewhat strange.

1095521093 is a prime number.
Neither 1095521092 nor 1095521094 are simple powers of 2.



---------------------------------------
Posted through http://www.FPGARelated.com
 
rahulkhikher wrote:
Hi,


Tools used by me : questa - 10.0c , xilinx - 13.2, ubuntu - 11.04.


I am trying to simulate GTX wrapper (generated from xilinx coregen) in
questasim. Steps followed by me :

1.Compliled the all xilinx library using "compxlibgui" in questasim.

2.Then copy the modelsim.in into the working directory of project.

3.launched the vsim with the "-L" switch for libraries and with -novopt



I am facing the following error while simulation:

....

# Refreshing
/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_data_gen_fifo
# Refreshing
/home/rahulk/scratch_rahulk/hw1/USB3dot0/regress/mylib.LINK_tb_rx_data_fifo

Fatal: (vsim-3421) Value 1095521093 for AC_CAP_DIS is out of range 0 to 1.
# Time: 0 fs Iteration: 0 Instance:
/LINK_test_tb/link_dut/v6_gx_for_link1/gtx0_v6_gtxwizard_v1_10_i/gtxe1_i
File: /tools/Xilinx/13.2/ISE_DS/ISE/vhdl/src/unisims/secureip/GTXE1.vhd
Line: 54
# FATAL ERROR while loading design
# Error loading design
Error loading design



I am able to simulate the same project in the ISIM.


Please replay me the solution of this issue.



Thanks,

Rahul




---------------------------------------
Posted through http://www.FPGARelated.com
Click to expand...
It looks like Questa is not properly decrypting the secureIP from
the Xilinx library. Have you checked with Xilinx to see if your
version of Questa supports their secureIP libraries? The malformed
generic could just be a symptom of improper decryption of the source.

--
Gabor
 
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