T
Thomas Bartzick
Guest
Hello everybody!
I have a problem with placing my tbuf-elements.
Modules using bus operations are coupled to top-level switching them
to a bidirectional bus. See, like this:
---<snip!>
entity my_struct is port (
...
BD : inout std_logic_vector(15 downto 0);
...);
end my_struct;
architecture Behavioral of my_struct is
....
signal de, di : std_logic_vector(15 downto 0);
....
begin
....
my_external_connector : process (de, BD, ext_read)
begin
if (ext_read = '1') then
BD <= de;
de <= "ZZZ...Z";
else
BD <= "ZZZ...Z";
de <= BD;
end if;
end process;
....
mod_databus_write_sync : SYNC_2xFF port map (
I => de,
O => di);
....
my_module : SOME_MODULE port map (
DIN => di,
DOUT => internal_output,
CS => ...,
...);
my_toplevel_bus_read_process: process (internal_output,
read_condition)
begin
if (read_condition = '1') then
de <= internal_output;
else
de <= "ZZZ...Z";
end if;
end process;
end Behavioral;
---<snap!>
Additional Note:
****************
There are about 3 upto 5 internal modules which make use of this
structure.
So we get a maximum of 5x16 = 80 tristate buffer lines, probably some
more.
****************
Synthezising, Translation and Mapping is always fine, but since the
implementation process comes to PAR, the placer stops after a couple
of warnings and at least one error like this:
---<snip!>
.... WARNING! Unable to place TBUF of module <#1>!
....
.... WARNING! Unable to place TBUF of module <#n>!
....
.... ERROR! Placing was not complete!
....
---<snap!>
I have read on XILINX support pages, that this problem can be worked
around by using AREA_GROUP constraints. If I have understood this in
the right way, the constraints will show the placer how I would like
to layout the tristate buffers. But all I can choose in ISE for
SPARTANII are Row and Column-statements, for which I have no idea how
to use them in a proper way.
I am using XILINX Webpack ISE 6.1 with a SPARTANII (-5) architecture.
Help or at least some hints would be very appreciated!
Bye,
Thomas.
I have a problem with placing my tbuf-elements.
Modules using bus operations are coupled to top-level switching them
to a bidirectional bus. See, like this:
---<snip!>
entity my_struct is port (
...
BD : inout std_logic_vector(15 downto 0);
...);
end my_struct;
architecture Behavioral of my_struct is
....
signal de, di : std_logic_vector(15 downto 0);
....
begin
....
my_external_connector : process (de, BD, ext_read)
begin
if (ext_read = '1') then
BD <= de;
de <= "ZZZ...Z";
else
BD <= "ZZZ...Z";
de <= BD;
end if;
end process;
....
mod_databus_write_sync : SYNC_2xFF port map (
I => de,
O => di);
....
my_module : SOME_MODULE port map (
DIN => di,
DOUT => internal_output,
CS => ...,
...);
my_toplevel_bus_read_process: process (internal_output,
read_condition)
begin
if (read_condition = '1') then
de <= internal_output;
else
de <= "ZZZ...Z";
end if;
end process;
end Behavioral;
---<snap!>
Additional Note:
****************
There are about 3 upto 5 internal modules which make use of this
structure.
So we get a maximum of 5x16 = 80 tristate buffer lines, probably some
more.
****************
Synthezising, Translation and Mapping is always fine, but since the
implementation process comes to PAR, the placer stops after a couple
of warnings and at least one error like this:
---<snip!>
.... WARNING! Unable to place TBUF of module <#1>!
....
.... WARNING! Unable to place TBUF of module <#n>!
....
.... ERROR! Placing was not complete!
....
---<snap!>
I have read on XILINX support pages, that this problem can be worked
around by using AREA_GROUP constraints. If I have understood this in
the right way, the constraints will show the placer how I would like
to layout the tristate buffers. But all I can choose in ISE for
SPARTANII are Row and Column-statements, for which I have no idea how
to use them in a proper way.
I am using XILINX Webpack ISE 6.1 with a SPARTANII (-5) architecture.
Help or at least some hints would be very appreciated!
Bye,
Thomas.