D
Dominik Fröhlich
Guest
Hello everybody,
has anyone of you experience how to use Spark-generated designs without
Synopsys tools? The generated designs heavily depend on the wired-or
resolution function, which is only provided by Synopsys, but not, for
instance, by XST or Synplicity, which do not support other resolution
functions than the one defined for std_logic at all.
The problem occurs everytime an inout-signal is required in the design,
e.g. for global variables, which may be written by multiple signal
sources. Usually, you could connect the signal sources by a bus.
However, the wiredOr-Type does, of course, not support 3-state.
I also tried to convert the wiredOr-types to appropriate
std_logic_vector types which are then connected by a bus. This works
fine for the signals written to the bus. But now there is a multi-source
on integer problem on the locals site.
Of course, the cleanest solution would be if the Spark generated code,
only used std_logic types. Nice wish.
Any comments or hints are welcome.
Regards
Dominik
has anyone of you experience how to use Spark-generated designs without
Synopsys tools? The generated designs heavily depend on the wired-or
resolution function, which is only provided by Synopsys, but not, for
instance, by XST or Synplicity, which do not support other resolution
functions than the one defined for std_logic at all.
The problem occurs everytime an inout-signal is required in the design,
e.g. for global variables, which may be written by multiple signal
sources. Usually, you could connect the signal sources by a bus.
However, the wiredOr-Type does, of course, not support 3-state.
I also tried to convert the wiredOr-types to appropriate
std_logic_vector types which are then connected by a bus. This works
fine for the signals written to the bus. But now there is a multi-source
on integer problem on the locals site.
Of course, the cleanest solution would be if the Spark generated code,
only used std_logic types. Nice wish.
Any comments or hints are welcome.
Regards
Dominik