Problem with Simulation

J

J M

Guest
I am trying to create a ring oscillator for an EE project. Whenever I try
to use the analog environment to simulate the design I keep running into
errors. Since I thought it might have been the cell library I tried
copying the tristate inverter and modifying it to test each type.

When I use the original design which is using nmos and pmos transistors
from the NCSU library it will not even netlist and simply provides an Mx
(where x is the number of the instance) has no information available.

I tried to change this by using the library listed under cadence as the
analogLib and using the pmos and nmos transistors from there. This will
create a netlist; however, when it goes to do the simulation it will once
again return errors about Mx. However this time the errors seem to
complain about something to do with their spice setup...

If anyone can provide any ideas to help me get this simulation working it
would be greatly appreciated.

Thank you.
 
It looks like you don't have any physical models of the devices. Look in
Spice under the settings whether you defined the necessary include files
with the bsim-models (depends on your technology)

Greetings,

Stefan

"J M" <joeyosu@yahoo.com> schrieb im Newsbeitrag
news:pan.2004.05.04.21.34.56.721915@yahoo.com...
I am trying to create a ring oscillator for an EE project. Whenever I try
to use the analog environment to simulate the design I keep running into
errors. Since I thought it might have been the cell library I tried
copying the tristate inverter and modifying it to test each type.

When I use the original design which is using nmos and pmos transistors
from the NCSU library it will not even netlist and simply provides an Mx
(where x is the number of the instance) has no information available.

I tried to change this by using the library listed under cadence as the
analogLib and using the pmos and nmos transistors from there. This will
create a netlist; however, when it goes to do the simulation it will once
again return errors about Mx. However this time the errors seem to
complain about something to do with their spice setup...

If anyone can provide any ideas to help me get this simulation working it
would be greatly appreciated.

Thank you.
Click to expand...
 
Hey

I am using Analog Environment of Cadence. Using virtuoso schematic I
am creating a small BJT amplifier.

Using HSpice as simulation tool.

During Simulation, it first gave me an error for generating a netlist
as my "modelname" in the properties of npn transistor is empty. I got
that NPN transistor instant from analogLib and so I wrote that name in
that place.

Now it is generating the netlist and giving an error due to model
name.

Please help to figure out whats the error and what can be done to do
things work out.

Regards
Chander.
 
the transistors from analogLib do not have
a simulation model. You have to have a model
file to run a simulation.

the model file is provided by your foundry. If you
do not have a design kit from a foundry you can
use the generic process design kit from cadence
at pdk.cadence.com, i think it does contain
simulation models.

stéphane

"Chander" <raosreeram@yahoo.co.in> wrote in message
news:68066c58.0405160219.21e679cc@posting.google.com...
Hey

I am using Analog Environment of Cadence. Using virtuoso schematic I
am creating a small BJT amplifier.

Using HSpice as simulation tool.

During Simulation, it first gave me an error for generating a netlist
as my "modelname" in the properties of npn transistor is empty. I got
that NPN transistor instant from analogLib and so I wrote that name in
that place.

Now it is generating the netlist and giving an error due to model
name.

Please help to figure out whats the error and what can be done to do
things work out.

Regards
Chander.
Click to expand...
 
Hi

Thankyou for your help S.Badel. I downloaded the NCSU CDK kit from
the NCSU website and where can I store the files that I got now. How I
have to proceed now?

Can anyone help me out what should be done to make my simulation work
out?

Thankyou in advance.

Chander.


"S. Badel" <stephane.badel@epfl.ch> wrote in message news:<40a88d1a$1@epflnews.epfl.ch>...
the transistors from analogLib do not have
a simulation model. You have to have a model
file to run a simulation.

the model file is provided by your foundry. If you
do not have a design kit from a foundry you can
use the generic process design kit from cadence
at pdk.cadence.com, i think it does contain
simulation models.

stéphane

"Chander" <raosreeram@yahoo.co.in> wrote in message
news:68066c58.0405160219.21e679cc@posting.google.com...
Hey

I am using Analog Environment of Cadence. Using virtuoso schematic I
am creating a small BJT amplifier.

Using HSpice as simulation tool.

During Simulation, it first gave me an error for generating a netlist
as my "modelname" in the properties of npn transistor is empty. I got
that NPN transistor instant from analogLib and so I wrote that name in
that place.

Now it is generating the netlist and giving an error due to model
name.

Please help to figure out whats the error and what can be done to do
things work out.

Regards
Chander.
Click to expand...
 
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