Problem with shift operation

I hav the follwoing simple code which does left shifting operation.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;



architecture counter of counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin

process(clock,reset)
begin

if reset='0' then
count<="0000";
elsif(clock='1') then
if en='1' then

l1: for i in 1 to 3 loop
count(i)<=q(i-1);
end loop l1;
count(0)<='0';

else
count<=q;
end if;
end if;
end process;
q<=count; -- The q value is not getting updated
with the count value.
end counter;

The problem with this code is that the q(port) value is not getting
updated with count value,though count gets updated.I did single step
execution,i see the statement q<=count being executed.I used the tool
Active HDL 4.2.PLEASE HELP....

 

[KJ]

Move the "q<=count;" statement outside of the process.

i.e..
process
.....
end process;

q<=count;

KJ

<Chandru.Kundagol@gmail.com> wrote in message
news:1145609945.305614.298370@e56g2000cwe.googlegroups.com...

I hav the follwoing simple code which does left shifting operation.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;



architecture counter of counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin

process(clock,reset)
begin

if reset='0' then
count<="0000";
elsif(clock='1') then
if en='1' then

l1: for i in 1 to 3 loop
count(i)<=q(i-1);
end loop l1;
count(0)<='0';

else
count<=q;
end if;
end if;
end process;
q<=count; -- The q value is not getting updated
with the count value.
end counter;

The problem with this code is that the q(port) value is not getting
updated with count value,though count gets updated.I did single step
execution,i see the statement q<=count being executed.I used the tool
Active HDL 4.2.PLEASE HELP....

 

[kunal]

u can try with variable. then it will update imediatly.
u can shif left like
temp := temp(2 downto 0) & data.
yhrough u can roatate also. it is easier than for loop.

 

[jens]

Are you sure you want a latch instead of a flip-flop? I assume not, in
which case replace

elsif(clock='1') then

with

elsif rising_edge(clock) then

and then everything should work better.