problem with shift left operations

[rekz]

My code is the following:

module ShiftLeft2(Input, Output);

input[31:0] Input;
output[31:0] Output;

always @(Input)
Output = Input << 2;
endmodule

and I am always getting this error:

Procedural assignment to a non-register <Output> is not permitted

why is this??

also is there a way to pass a wire value shifted to the left by 2 to
as a parameter.. for example:

AddALU Add(Test1, (SLRes << 2) ,Test2 , Test3);

so I don't have to create this module

 

[fpgabuilder]

On Mar 2, 1:22 pm, rekz <aditya15...@gmail.com> wrote:

My code is the following:

module ShiftLeft2(Input, Output);

input[31:0] Input;
output[31:0] Output;

always @(Input)
        Output = Input << 2;
endmodule

and I am always getting this error:

Procedural assignment to a non-register <Output> is not permitted

why is this??

also is there a way to pass a wire value shifted to the left by 2 to
as a parameter.. for example:

AddALU Add(Test1, (SLRes << 2) ,Test2 , Test3);

so I don't have to create this module

You need to declare Output as a register. Wires cannot be used inside
a procedural block i.e. always block.

 

[rekz]

On Mar 2, 2:28 pm, fpgabuilder <parekh...@gmail.com> wrote:

On Mar 2, 1:22 pm, rekz <aditya15...@gmail.com> wrote:





My code is the following:

module ShiftLeft2(Input, Output);

input[31:0] Input;
output[31:0] Output;

always @(Input)
        Output = Input << 2;
endmodule

and I am always getting this error:

Procedural assignment to a non-register <Output> is not permitted

why is this??

also is there a way to pass a wire value shifted to the left by 2 to
as a parameter.. for example:

AddALU Add(Test1, (SLRes << 2) ,Test2 , Test3);

so I don't have to create this module

You need to declare Output as a register.  Wires cannot be used inside
a procedural block i.e. always block.

I revised the code to the following:

module ShiftLeft2(in, out);

input [31:0] in;
output [31:0] out;
reg [31:0] out;
out = { in[29:0], 1'b0, 1'b0 };

endmodule

and I am getting:
out is not a type

why is this?

 

[David Rogoff]

You are also insane if you use ports (or signals) named Output and
Input. input and output (lowercase) are reserved symbols in Verilog.
Having signals that are the same name, except of case, is really asking
for trouble. And heaven help you if you end up with mixed Verilog/VHDL
sims since VHDL isn't case-sensitive.

David

On 2010-03-02 14:51:57 -0800, glen herrmannsfeldt said:

rekz <aditya15417@gmail.com> wrote:
(snip)

module ShiftLeft2(Input, Output);
input[31:0] Input;
output[31:0] Output;
always @(Input)
Output = Input << 2;
endmodule

and I am always getting this error:

Procedural assignment to a non-register <Output> is not permitted

Either make Output a reg, or, my preference, use continuous assign.

assign Output = Input << 2;

why is this??

also is there a way to pass a wire value shifted to the
left by 2 to as a parameter.. for example:

AddALU Add(Test1, (SLRes << 2) ,Test2 , Test3);

Yes you can do that.

so I don't have to create this module

(snip)

I revised the code to the following:

module ShiftLeft2(in, out);

input [31:0] in;
output [31:0] out;
reg [31:0] out;
out = { in[29:0], 1'b0, 1'b0 };

If this is a continuous assignment, then it needs the assign
keyword. (and without reg.)

If not, it needs to be inside a block, such as always.

I would probably use {in[29:0],2'b00} instead, but either works.

-- glen

 

[glen herrmannsfeldt]

rekz <aditya15417@gmail.com> wrote:
(snip)

module ShiftLeft2(Input, Output);
input[31:0] Input;
output[31:0] Output;
always @(Input)
Output = Input << 2;
endmodule

and I am always getting this error:

Procedural assignment to a non-register <Output> is not permitted

Either make Output a reg, or, my preference, use continuous assign.

assign Output = Input << 2;

why is this??

also is there a way to pass a wire value shifted to the
left by 2 to as a parameter.. for example:

AddALU Add(Test1, (SLRes << 2) ,Test2 , Test3);

Yes you can do that.

so I don't have to create this module

(snip)

I revised the code to the following:

module ShiftLeft2(in, out);

input [31:0] in;
output [31:0] out;
reg [31:0] out;
out = { in[29:0], 1'b0, 1'b0 };

If this is a continuous assignment, then it needs the assign
keyword. (and without reg.)

If not, it needs to be inside a block, such as always.

I would probably use {in[29:0],2'b00} instead, but either works.

-- glen