Problem with post-route simulation

[aleksa]

The whole ISE project (VHDL) can be found here:
http://www.mediafire.com/?wvvvcjrjl67lcnr

Besides ISE project, it also contains two print-screen GIFs,
behavioral.gif and post-route.gif.

behavioral.gif shows
@40ns : start = 1, data = AAAA
at next rising CLK edge CS goes LOW
then, SDI serially transmits data (101010...)
finally, CS goes HIGH (215ns)

That is exactly what I would expect from the VHDL code.

But the post-route.gif shows something completely
different, and I don't know why.

What am I doing wrong?

 

[aleksa]

http://img826.imageshack.us/img826/3067/designp.gif
This GIF shows how I actually start the simulator.

If I select "tb - behavior (tb.vhd)" in the upper section
(and double click Simulate Behavioral Model below)
I get the results of behavioral.gif

If I select "uut - DAC_STATE...so on" i get all signals as U, but, as
a bonus,
I do get internal signals in the list, which I don't get otherwise.

Really annoying..

 

[aleksa]

As Gabor suggested (in the Xilinx forums), post-route requires 100ns
delay for the GSR.
After changing the first line to "wait for 140 ns;" it now works.
Thanks Gabor, once again.

As for the internal signals, that is for another thread.

 

[aleksa]

Ok, if someone else has problems with internal signals, this is how I
do it now:

in this GIF http://img826.imageshack.us/img826/3067/designp.gif
use "tb - behavior (tb.vhd)", NOT "uut - DAC_STATE...so on.."

to view internal signals, open Instances and processes panel (and
Objects, of course)
open "tb", and click on "uut" to see internal signals,
as shown here http://img834.imageshack.us/img834/4431/inernalbehavioral.gif
drag signals and click on Re-launch.

I'm not saying this is the way to go, but I'm using it now.