Problem with operation

I hav the follwoing simple code which does left shifting operation.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;


architecture counter of counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin


process(clock,reset)
begin


if reset='0' then
count<="0000";
elsif(clock='1') then
if en='1' then


l1: for i in 1 to 3 loop
count(i)<=q(i-1);
end loop l1;
count(0)<='0';


else
count<=q;
end if;
end if;
q<=count; -- The q value is not getting updated with
the count
value.
end process;


end counter;


The problem with this code is that the q(port) value is not getting
updated with count value,though count gets updated.I did single step
execution,i see the statement q<=count being executed.I used the tool
Active HDL 4.2.PLEASE HELP....

 

[KJ]

Move the "q<=count;" statement outside of the process.

i.e..
process
.....
end process;

q<=count;

KJ

<Chandru.Kundagol@gmail.com> wrote in message
news:1145608936.787933.216740@e56g2000cwe.googlegroups.com...

I hav the follwoing simple code which does left shifting operation.

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;


architecture counter of counter is
signal count:std_logic_vector(3 downto 0):="0000";
begin


process(clock,reset)
begin


if reset='0' then
count<="0000";
elsif(clock='1') then
if en='1' then


l1: for i in 1 to 3 loop
count(i)<=q(i-1);
end loop l1;
count(0)<='0';


else
count<=q;
end if;
end if;
q<=count; -- The q value is not getting updated with
the count
value.
end process;


end counter;


The problem with this code is that the q(port) value is not getting
updated with count value,though count gets updated.I did single step
execution,i see the statement q<=count being executed.I used the tool
Active HDL 4.2.PLEASE HELP....

 

[KJ]

The other problem is that 'q' is defined to be a bi-directional signal but
nowhere in the architecture is 'q' ever set to a weak (and therefore
overridable) value such as 'Z'. In fact 'q' is always being actively driven
by 'counter' which means it really is an output only (VHDL type 'buffer'
since it is read from within the architecture as well). This implies that
there is no way to input anything into 'counter' to initialize 'q' at all.

If 'q' really does need to be bi-directional for some reason, then there has
to be some other control input signal that tells the entity when 'q' is an
input and when it's an output. When it's being used as an input than the
entity should be driving 'q <= (others => 'Z')'. The logic for loading
should also then look at this new input to tell it when it should be loading
from 'q' or when it should be shifting.

The other alternative is that there should simply be a 'd' input vector and
a 'q' output vector and data gets loaded from 'd'.

entity counter is
port (
q: inout STD_LOGIC_VECTOR (3 downto 0);
clock: in STD_LOGIC;
reset: in STD_LOGIC;
en: in STD_LOGIC
);
end counter;

KJ

 

[Hilko]

If you want to trigger your process with a rising slope of signal
"clock" then change the line
"elsif(clock='1') then" with "elsif rising_edge(clock) then"

Hilko

 

[Andy]

Try

process (reset, clock) is
begin
if reset = '0' then
q <= (others => '0');
elsif rising_edge(clock) then
if en = '1' then
q <= q(2 downto 0) & '0';
end if;
end if;
end process;


No need for intermediate signal/variable.

Andy