Problem with Netlist simulation.

[pallav]

I have a small design that I synthesized using Synopsys DC compiler
and mapped onto a target technology. I'm trying to simulate the
synthesized netlist on my regression tests but I'm having a problem I
don't seem to understand.

The top-level file that contains the the netlist is shown here:
http://www.pastey.net/125038

At the bottom of the file, I also give an example of the Verilog model
for the DFF that has been supplied by the technology. I ran my
simulation first on Synopsys VCS. If I include the `define functional
flag in my netlist, the simulation passes on VCS. However, if I remove
this flag, I get a bunch of setup time violations and simulation just
hangs (it is running forever). They look as follows:

"../ref/verilog/DFFX2.v", 50: Timing violation in
mips32_tb.U0.cpu.datapath_r2D_q_reg_8_
$setup( posedge D:65055, posedge CLK:65059, limit: 80 );

"../ref/verilog/DFFX2.v", 50: Timing violation in
mips32_tb.U0.cpu.datapath_r2D_q_reg_7_
$setup( posedge D:65055, posedge CLK:65059, limit: 80 );

I looked at the synthesized timing reports and all the paths had
positive or 0 slack so there didn't seem to be violations. The
constraints I gave were a 10 ns clock with clock latency of 1.5. In my
testbench, I have a clock period set to 10.

I tried this netlist on Icarus Iverilog. Here the reverse is true. If
I keep `define functional, the simulation hangs (runs forever).
However, if I remove this flag, the simulation passes.

Does anyone have any idea what is going on here? I am using gated
clocks on the flip flops so could that be causing the setup
violations? Even then, I'm not sure why VCS/Iverilog behaving
differently.

module SNPS_CLOCK_GATE_HIGH_dflopenrc_WIDTH32_0 ( CLK, EN, ENCLK );
input CLK, EN;
output ENCLK;
wire net2700, net2701;

AND2X1 main_gate ( .IN1(net2700), .IN2(CLK), .Q(ENCLK) );
LATCHX2 latch ( .CLK(net2701), .D(EN), .Q(net2700), .QN() );
AOINVX1 U1 ( .IN(CLK), .QN(net2701) );
endmodule

DFFX2 datapath_r2D_q_reg_7_ ( .D(n3179), .CLK(datapath_r2D_net2707), .Q
(datapath_signimmD[7]), .QN() );

SNPS_CLOCK_GATE_HIGH_dflopenrc_WIDTH32_0 datapath_r2D_clk_gate_q_reg
( .CLK(
clk), .EN(datapath_r2D_net2703), .ENCLK
(datapath_r2D_net2707) );


Thanks for any ideas.

Kind regards.