Problem with multiple constant drivers

[Carlos Barberis]

Hello,
I am trying to put together a simple one shot counter that gets trigered
once every time an input signal (Gate) the counter just counts to some
preloaded value and then just stops counting till the next time

Because I am a Verilog neophite I seem to struggle with the following error
while using Altera Quartus:

Error (10028): Can't resolve multiple constant drivers for net "temp" at
PulseWidthCounter.v(25)

Any help or sugestions will greatly appreciated!!!

The code is as follows:
************************************************** ****************
module PulseWidthCounter(clk,CountVal,counterenable,Gate, PulseOut);

parameter SIZE = 20;
input clk;
input Gate;
input counterenable;
input [SIZE - 1:0]CountVal;
output PulseOut = 0;
reg [SIZE - 1:0]CounterVal;
reg [SIZE - 1:0]clk1;
reg PulseOut;
reg temp = 0;

always @ (posedge counterenable)begin CounterVal <= CountVal; end
always @ (posedge Gate)begin temp <= 1'b1; end

always @ (posedge clk)
begin

if(temp == 1'b1)begin

clk1 <= clk1 +1;
if (clk1 < CounterVal)
PulseOut <= 1'b1;
else
PulseOut <= 1'b0; clk1 <=0; temp <= 0; end


end

endmodule

 

[gabor]

On Nov 4, 10:04 am, "Carlos Barberis" <car...@bartek.com> wrote:

Hello,
I am trying to put together a simple one shot counter that gets trigered
once every time an input signal (Gate) the counter just counts to some
preloaded value and then just stops counting till the next time

Because I am a Verilog neophite I seem to struggle with the following error
while using Altera Quartus:

Error (10028): Can't resolve multiple constant drivers for net "temp" at
PulseWidthCounter.v(25)

Any help or sugestions will greatly appreciated!!!

The code is as follows:
************************************************** ****************
module PulseWidthCounter(clk,CountVal,counterenable,Gate, PulseOut);

parameter SIZE = 20;
input clk;
input Gate;
input counterenable;
input [SIZE - 1:0]CountVal;
output PulseOut = 0;
reg [SIZE - 1:0]CounterVal;
reg [SIZE - 1:0]clk1;
reg PulseOut;
reg temp = 0;

always @ (posedge counterenable)begin CounterVal <= CountVal; end
always @ (posedge Gate)begin temp <= 1'b1; end

always @ (posedge clk)
begin

if(temp == 1'b1)begin

clk1 <= clk1 +1;
if (clk1 < CounterVal)
PulseOut <= 1'b1;
else
PulseOut <= 1'b0; clk1 <=0; temp <= 0; end

end

endmodule

Although you may be able to simulate this code, for Synthesis
you need to drive each register from no more than one always
block. Your "temp" register is driven in two such blocks.
This defines a register with two separate edge-triggered
clocks, which cannot be implemented in the hardware. You may
want to use a synchronized version of the gate signal in
your other clocked process. In any case, since clk is
presumably not synchronous to the edges of Gate, making
an edge-triggered enable signal won't help to generate
a constant delay to your start of the output pulse.

A more common approach is to synchronize and delay the Gate
input with two flip-flop stages using clk. Then start your
count when the first stage is high and the second stage low
indicating a rising edge has recently happened on Gate.

If you need the pulse to start immediately upon the rising
edge of Gate, you can create a separate process where Gate
clocks the pulse high, and some decoded terminal count signal
resets the pulse low asynchronously.