problem with modelsim

[sravan reddy]

hello ,

when i was trying to simulate my vhdl code usign modelsim , all the
signals are converted into small case ,
for example if my signal was Q(capital) it will be converted into
q(small)
is there any procedure to keep the signals as it is , without changing
the case.

 

[Mike Treseler]

sravan reddy wrote:

when i was trying to simulate my vhdl code usign modelsim , all the
signals are converted into small case ,
for example if my signal was Q(capital) it will be converted into
q(small)
is there any procedure to keep the signals as it is , without changing
the case.

There may be, but consider the a possible side effect
of a mixed case naming convention. If I happen to misspell
my_outQ as my_outq in my code, my vhdl tools will
not notice the difference. If I or someone else
reuses the same code and does a search and replace
to rename my_outQ, he may or may not find
all of the identifiers.


-- Mike Treseler

 

[Weng Tianxiang]

This is an old problem that ModelSim never pays attention to and always
turns a dead ear to it.

I use signal naming rule as in C, like DMAChainEndIntEnable_b6, you
cannot recognize it in all small cases when doing simulation with
ModelSim.

Weng

 

[sravan reddy]

thanks sir for the reply

sravan reddy

 

[sravan reddy]

thanks sir for the reply

sravan reddy