Problem with loops in testbench

[Alireza]

Hello ,
I tried to use the following loop to build allpossible cases for my 4
bit adder.but when simulation it goes to infinte loop.what is the
problem?
module test;
wire c,cout,s,out;
reg a,b,sw,carry;
reg[3:0] a1,a2;
wire[3:0] sum;
wire[3:0] result;
hAdd h(c,s,a,b);
fullAdder_4 adder(cout,sum,a1,a2);
always begin
$monitor($time," a:%d b:%d cout,sum:%d ",a1,a2,{cout,sum});
a1=0;
a2=0;
for(a1=0 ; a1 <= 15; a1 = a1 + 1)
begin
#100 for(a2=0 ; a2 <= 15; a2 = a1 + 1)
#100;
end

#100 $finish;
end
endmodule

 

[John_H]

Alireza wrote:

Hello ,
I tried to use the following loop to build allpossible cases for my 4
bit adder.but when simulation it goes to infinte loop.what is the
problem?
module test;
wire c,cout,s,out;
reg a,b,sw,carry;
reg[3:0] a1,a2;
wire[3:0] sum;
wire[3:0] result;
hAdd h(c,s,a,b);
fullAdder_4 adder(cout,sum,a1,a2);
always begin
$monitor($time," a:%d b:%d cout,sum:%d ",a1,a2,{cout,sum});
a1=0;
a2=0;
for(a1=0 ; a1 <= 15; a1 = a1 + 1)
begin
#100 for(a2=0 ; a2 <= 15; a2 = a1 + 1)
#100;
end

#100 $finish;
end
endmodule

Try a2 = a2 + 1 rather than a2 = a1 + 1 as you have specified in the
second loop.

 

[Stephen Williams]

Alireza wrote:

Hello ,
I tried to use the following loop to build allpossible cases for my 4
bit adder.but when simulation it goes to infinte loop.what is the
problem?
module test;
wire c,cout,s,out;
reg a,b,sw,carry;
reg[3:0] a1,a2;
wire[3:0] sum;
wire[3:0] result;
hAdd h(c,s,a,b);
fullAdder_4 adder(cout,sum,a1,a2);
always begin
$monitor($time," a:%d b:%d cout,sum:%d ",a1,a2,{cout,sum});
a1=0;
a2=0;
for(a1=0 ; a1 <= 15; a1 = a1 + 1)
begin
#100 for(a2=0 ; a2 <= 15; a2 = a1 + 1)
#100;
end

#100 $finish;
end
endmodule

Two problems. First, the increment expression for the inner loop
appears wrong. Fix that.

Second, ask yourself what (15+1) is when shoved into a 4-bit a1 or
a2 variable. (The latter is a common error.)


--
Steve Williams "The woods are lovely, dark and deep.
steve at icarus.com But I have promises to keep,
http://www.icarus.com and lines to code before I sleep,
http://www.picturel.com And lines to code before I sleep."

 

[Ajeetha (www.noveldv.com)]

On Apr 3, 4:01 pm, "Alireza" <foola...@gmail.com> wrote:

Hello ,
I tried to use the following loop to build allpossible cases for my 4
bit adder.but when simulation it goes to infinte loop.what is the
problem?

SNIP>>>

always begin
$monitor($time," a:%d b:%d cout,sum:%d ",a1,a2,{cout,sum});

Why do you need always block here? Replace it first with initial. Also
try what John suggested.

Regards
Ajeetha, CVC
www.noveldv.com

 

hi
always without sensitive list gives infinite execution time


Alireza wrote:

Hello ,
I tried to use the following loop to build allpossible cases for my 4
bit adder.but when simulation it goes to infinte loop.what is the
problem?
module test;
wire c,cout,s,out;
reg a,b,sw,carry;
reg[3:0] a1,a2;
wire[3:0] sum;
wire[3:0] result;
hAdd h(c,s,a,b);
fullAdder_4 adder(cout,sum,a1,a2);
always begin
$monitor($time," a:%d b:%d cout,sum:%d ",a1,a2,{cout,sum});
a1=0;
a2=0;
for(a1=0 ; a1 <= 15; a1 = a1 + 1)
begin
#100 for(a2=0 ; a2 <= 15; a2 = a1 + 1)
#100;
end

#100 $finish;
end
endmodule

 

[Alex]

On Apr 5, 2:59 am, thiyagu2...@yahoo.co.in wrote:

hi
always without sensitive list gives infinite execution time

In fact, for this example, always is the same as initial.
The first execution of always block happens at 0 simulation time;
since there is $finish inside the process, it is executed only once.

It still does not mean that there is a need to use "always" instead of
"initial"

-Alex