Problem with JTAG_SIM_VIRTEX4

[Stefan Hauf]

Hello,

i have a problem using the JTAG_SIM_VIRTEX4 block from Xilinx. I am
able to send data to the BSCAN block in the design but cannot readout
data from the BSCAN block. I discoverd that the jtag_instruction_name
is set to IDCODE in the beginning, after shifting some bits into the
register always switches to UNKNOWN.
Did anyone use this function successfully?

BR Stefan

 

[Stefan Hauf]

Hi,

I solved the probem on my own.
In the unisim source i found the pattern (14bit) to get in the right
state. In the application note only the last 5 bits are mentioned.

BR
Stefan