Problem with Cadence AMS simulator

G

Guneet Singh

Guest
Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
../ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
committing in the whole process.

Thanks and regards,
Guneet
 
guneet_it@yahoo.com (Guneet Singh) wrote in message news:<f01c79c9.0312142308.4e5d5a26@posting.google.com>...
Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
Click to expand...
I don't know much about this, but this looks wrong. Why is it
reporting an error in an hdl.var file when you are working with
the cds.lib files? They are supposed to be separate things.


cds.lib files:
...
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
Click to expand...

I would guess that this is your problem. It looks like your own
cds.lib file is explicitly including an hdl.var file. I've never
been clear on what goes in these files, but I am pretty sure that
a cds.lib file should not be including an hdl.var file. That
include should probably go in ./hdl.var instead.

If you wrote this ./cds.lib file yourself, then this is probably
your mistake. If it got generated by the installation process
somehow, then I don't have any idea what is wrong. Personally,
I have never written a cds.lib or hdl.var file. I just use what
ncprep creates for me, possibly modifying it slightly.

I also notice that you are using a rather old release of the
software. Recent versions will allow you to leave out the cds.lib
and hdl.var files if you don't want anything but the defaults.
 
Do you have a ' (tick) in front of the DEFINE like what you would do in
Verilog? If so, you should not -- it should just start with DEFINE.

"Guneet Singh" <guneet_it@yahoo.com> wrote in message
news:f01c79c9.0312142308.4e5d5a26@posting.google.com...
Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
committing in the whole process.

Thanks and regards,
Guneet
Click to expand...
 
Guneet Singh wrote:
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
Click to expand...
These statements belong to the hdl.var file, not to the cds.lib file. So
you have to move them into the hdl.var file.

-Eyck
 
Hello everyone,
Thanks a lot for the responses. I am indeed very grateful for
that. I have got LDV-5.1 installed and am in the process of getting
the license matters resolved.
For the time being, I am working on AMS-2.0 (trying to get it
running before we get the license for LDV-5.1) and am getting the
following error(s) on executing the ncsim command:

ncsim -amslic -analogcontrol ancont.scs res1
ncsim: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Click to expand...
Systems, Inc.

Analog Kernel using -ANALOGCONTROL ancont.scs.
ERROR! cdsInit has not been called
ERROR! can't determine installation root from PATH
ncsim: *internal* (rts_seghandler - SIGSEGV unexpected violation
pc=0xfeab2fb0 addr=0x00000000).

It would be very helpful if someone could throw some light on this.

Thanks again,
Guneet Singh


Eyck Jentzsch <jentzsch@cadence.com> wrote in message news:<3fdea302$1@news.cadence.com>...
Guneet Singh wrote:
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of

These statements belong to the hdl.var file, not to the cds.lib file. So
you have to move them into the hdl.var file.

-Eyck
Click to expand...
 
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