Problem with Cadence AMS simulator

G

Guneet Singh

Guest
Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
../ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
making in the whole process.

Thanks and regards,
Guneet
 
Guneet,

From the error messages, I would guess that you have an INCLUDE or a SOFTINCLUE
in your cds.lib file which is including an hdl.var file. That's not the correct
thing to do. An hdl.var file (whilst similar syntax) needs to be kept separate
from the cds.lib file.

I managed to get similar error messages by doing the above.

You didn't actually post your cds.lib file, so it's hard to be certain, but
this seems a likely explanation to me.

Also, AMS20 is a rather early version of AMS Designer, and I'd definitely
recommend moving to a newer one (e.g. LDV51) if you can. Things have
moved on a lot in AMS Designer.

Regards,

Andrew.

On 14 Dec 2003 23:06:56 -0800, guneet_it@yahoo.com (Guneet Singh) wrote:

Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
making in the whole process.

Thanks and regards,
Guneet
Click to expand...
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
Hello,
Thanks a lot for the responses both here and on the
www.designers-guide.com Verilog forum. I am very grateful to you for
that. As suggested, I have got LDV-5.1 installed and am in the process
of getting the license matters resolved.
For the time being, I am still trying to get AMS-2.0 running so
that I could so do something on it before making the switch to LDV
5.1.
I am getting the following error(s) on executing the ncsim
command:

ncsim -amslic -analogcontrol ancont.scs res1
ncsim: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Click to expand...
Systems, Inc.

Analog Kernel using -ANALOGCONTROL ancont.scs.
ERROR! cdsInit has not been called
ERROR! can't determine installation root from PATH
ncsim: *internal* (rts_seghandler - SIGSEGV unexpected violation
pc=0xfeab2fb0 addr=0x00000000).


I have the following paths specified in my startup file:

setenv LD_LIBRARY_PATH
\${LD_LIBRARY_PATH}:/opt/CAD/Cadence/AMS-2.0/tools/lib
set path = (/opt/CAD/Cadence/AMS-2.0/tools/bin $path)
set path = (/opt/CAD/Cadence/AMS-2.0/tools/inca/bin $path)

Do I need to make some changes to the the .cdsinit file in the
Cadence install directory?
It would be extremely helpful if you could suggest me what to do
from here.
Thanks again,
Guneet Singh



Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<v04ttv42r2vdafq7rpi07m1cf3ukenuuup@4ax.com>...
Guneet,

From the error messages, I would guess that you have an INCLUDE or a SOFTINCLUE
in your cds.lib file which is including an hdl.var file. That's not the correct
thing to do. An hdl.var file (whilst similar syntax) needs to be kept separate
from the cds.lib file.

I managed to get similar error messages by doing the above.

You didn't actually post your cds.lib file, so it's hard to be certain, but
this seems a likely explanation to me.

Also, AMS20 is a rather early version of AMS Designer, and I'd definitely
recommend moving to a newer one (e.g. LDV51) if you can. Things have
moved on a lot in AMS Designer.

Regards,

Andrew.

On 14 Dec 2003 23:06:56 -0800, guneet_it@yahoo.com (Guneet Singh) wrote:

Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
making in the whole process.

Thanks and regards,
Guneet
Click to expand...
 
Hi Guneet,

Not sure whether the segmentation fault is caused by this, but you
shouldn't need the tools/inca/bin in the path - this may well be what is
causing the cdsInit problem, and not being able to determine installation
root.

Regards,

Andrew.

On 23 Dec 2003 01:35:13 -0800, guneet_it@yahoo.com (Guneet Singh) wrote:

Hello,
Thanks a lot for the responses both here and on the
www.designers-guide.com Verilog forum. I am very grateful to you for
that. As suggested, I have got LDV-5.1 installed and am in the process
of getting the license matters resolved.
For the time being, I am still trying to get AMS-2.0 running so
that I could so do something on it before making the switch to LDV
5.1.
I am getting the following error(s) on executing the ncsim
command:

ncsim -amslic -analogcontrol ancont.scs res1
ncsim: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.

Analog Kernel using -ANALOGCONTROL ancont.scs.
ERROR! cdsInit has not been called
ERROR! can't determine installation root from PATH
ncsim: *internal* (rts_seghandler - SIGSEGV unexpected violation
pc=0xfeab2fb0 addr=0x00000000).


I have the following paths specified in my startup file:

setenv LD_LIBRARY_PATH
\${LD_LIBRARY_PATH}:/opt/CAD/Cadence/AMS-2.0/tools/lib
set path = (/opt/CAD/Cadence/AMS-2.0/tools/bin $path)
set path = (/opt/CAD/Cadence/AMS-2.0/tools/inca/bin $path)

Do I need to make some changes to the the .cdsinit file in the
Cadence install directory?
It would be extremely helpful if you could suggest me what to do
from here.
Thanks again,
Guneet Singh



Andrew Beckett <andrewb@DELETETHISBITcadence.com> wrote in message news:<v04ttv42r2vdafq7rpi07m1cf3ukenuuup@4ax.com>...
Guneet,

From the error messages, I would guess that you have an INCLUDE or a SOFTINCLUE
in your cds.lib file which is including an hdl.var file. That's not the correct
thing to do. An hdl.var file (whilst similar syntax) needs to be kept separate
from the cds.lib file.

I managed to get similar error messages by doing the above.

You didn't actually post your cds.lib file, so it's hard to be certain, but
this seems a likely explanation to me.

Also, AMS20 is a rather early version of AMS Designer, and I'd definitely
recommend moving to a newer one (e.g. LDV51) if you can. Things have
moved on a lot in AMS Designer.

Regards,

Andrew.

On 14 Dec 2003 23:06:56 -0800, guneet_it@yahoo.com (Guneet Singh) wrote:

Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for
Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I
am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design
Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC (
./ncsimrc, ~/.ncsimrc )' on line 4 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX
( .vhd, .vhdl )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE
VERILOG_SUFFIX ( .v )' on line 5 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\
/opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib


I would be grateful if someone could point out the mistake I am
making in the whole process.

Thanks and regards,
Guneet
Click to expand...
--
Andrew Beckett
Senior Technical Leader
Custom IC Solutions
Cadence Design Systems Ltd
 
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