Problem with asynchronous reset mysteriously setting up outp

[Pedro Lazaro]

Greetings,

I would be grateful if you could help me on this problem.

FIRST,
I have this code below:
--------------------------------------------
module timer(
input clk,
input reset,
output reg signal // <--- PROBLEMATIC SIGNAL
);

always@(posedge clk or posedge reset)
begin
if(reset)
signal <= 1;
else
signal <= 0;
end
endmodule
--------------------------------------------

and this testbench, which was executed on modelsim:
--------------------------------------------
`timescale 1ns / 1ps
`define PERIOD 20

module timer_tb;
logic clk;
logic reset;
logic signal;

timer inst(
.clk(clk),
.reset(reset),
.signal(signal)
);

initial
begin
clk = 0;
forever clk = #(`PERIOD/2) ~clk;
end

initial
begin
reset = 0; //<--- RESET STARTS CLEANED.
#(`PERIOD)
reset = 1;
#(`PERIOD)
reset = 0;
#(`PERIOD*3)
reset = 1;
#(`PERIOD)
reset = 0;

#(`PERIOD*3)
$display("End of the simulation");
$stop;
end
endmodule
------------------------------------------------------
SO, THE PROBLEM:
=========
Output reg "signal" starts HIGH but in the code, this reg depends of reset, and the reset starts DOWN.

I don't understand why "signal" register is HIGH in the beginning of the simulation as the reset starts surely DOWN.

I need the "signal" starting DONW and only be set up IF reset go to 1 (condition posedge reset just like my code).
=========

Please take a look on this print of the waveform for clear understanding of my problem:

WAVEFORM ON MODELSIM IMAGE: http://postimg.org/image/5wktylub9/

Thank you for your attention.

Pedro

 

[GaborSzakacs]

Pedro Lazaro wrote:

Greetings,

I would be grateful if you could help me on this problem.

FIRST,
I have this code below:
--------------------------------------------
module timer(
input clk,
input reset,
output reg signal // <--- PROBLEMATIC SIGNAL
);

always@(posedge clk or posedge reset)
begin
if(reset)
signal <= 1;
else
signal <= 0;
end
endmodule
--------------------------------------------

and this testbench, which was executed on modelsim:
--------------------------------------------
`timescale 1ns / 1ps
`define PERIOD 20

module timer_tb;
logic clk;
logic reset;
logic signal;

timer inst(
.clk(clk),
.reset(reset),
.signal(signal)
);

initial
begin
clk = 0;
forever clk = #(`PERIOD/2) ~clk;
end

initial
begin
reset = 0; //<--- RESET STARTS CLEANED.
#(`PERIOD)
reset = 1;
#(`PERIOD)
reset = 0;
#(`PERIOD*3)
reset = 1;
#(`PERIOD)
reset = 0;

#(`PERIOD*3)
$display("End of the simulation");
$stop;
end
endmodule
------------------------------------------------------
SO, THE PROBLEM:
=========
Output reg "signal" starts HIGH but in the code, this reg depends of reset, and the reset starts DOWN.

I don't understand why "signal" register is HIGH in the beginning of the simulation as the reset starts surely DOWN.

I need the "signal" starting DONW and only be set up IF reset go to 1 (condition posedge reset just like my code).
=========

Please take a look on this print of the waveform for clear understanding of my problem:

WAVEFORM ON MODELSIM IMAGE: http://postimg.org/image/5wktylub9/

Thank you for your attention.

Pedro

For behavioral simulation, signal should start as unknown or 'X'. If
it is starting at 1, I expect you are running a post-translate
simulation. In this case the synthesis tools are allowed to treat
that 'X' as either 0 or 1 based on what's easiest. If you need the
signal to start 0, then you should put it in the declaration like:

output reg signal = 0

Note that for an FPGA, this might be a problem if the startup and
asynchronous reset values cannot differ. This is the case with
Spartan 6 and newer Xilinx FPGA's, while earlier ones allowed the
initial value and reset value to be different.

--
Gabor

 

[SysTom]

I agree with Gabor that this is not precisely the code that is simulated, because there is a pronounced clock-to-Q output delay on signal 'signal' which is not present in the RTL above. When I simulate your code above (Modelsim SE 6.6f; Thanks for the complete code BTW) I get the proper expected behavior with 'signal' starting X, going low with first posedge 'clk', then high with posedge 'reset'. Your code is simple enough (even if gate-level netlist) to debug by starting at time t=0, and single stepping into each statement/event that causes a change to see how it could possibly end up high after X.