Problem with analysis of the low noise preamplifier circuit

[Archer]

Hello all,
I am making a low noise preamplifier with JFET, but i can't understand
and calculate the pointed section of this graphics:
http://archer.3322.org/webtest/problem%20of%20jfet%20amp.GIF

The work point of this section is so difficult to determined that i can't
adjust the Resistence for
my own. who can help me with this troubled problem.

 

[Ian Bell]

Archer wrote:

Hello all,
I am making a low noise preamplifier with JFET, but i can't understand
and calculate the pointed section of this graphics:
http://archer.3322.org/webtest/problem%20of%20jfet%20amp.GIF

The work point of this section is so difficult to determined that i can't
adjust the Resistence for
my own. who can help me with this troubled problem.

The link does not seem to be working.

Ian

 

[Archer]

this would be better
http://www.chinastudygroup.org/b2/index.php?p=46&more=1&c=1&tb=1&pb=1
"Ian Bell" <itb@yahoo.com> Đ´ČëÓĘźţ
news:c4cdr4$2g3hm1$5@ID-225948.news.uni-berlin.de...

Archer wrote:

Hello all,
I am making a low noise preamplifier with JFET, but i can't
understand
and calculate the pointed section of this graphics:
http://archer.3322.org/webtest/problem%20of%20jfet%20amp.GIF

The work point of this section is so difficult to determined that i
can't
adjust the Resistence for
my own. who can help me with this troubled problem.

The link does not seem to be working.

Ian

 

[Kevin Aylward]

Archer wrote:

this would be better
http://www.chinastudygroup.org/b2/index.php?p=46&more=1&c=1&tb=1&pb=1
"Ian Bell" <itb@yahoo.com> Đ´ČëÓĘźţ

No its not. There is no schematic. Do you actually test your links?

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Archer]

I can see it on my ie,perhaps it's because of the net which the pic was in.
I sign up a virtual host,this would work well.
http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:fjwac.7$WU2.0@newsfep3-gui.server.ntli.net...

Archer wrote:
this would be better
http://www.chinastudygroup.org/b2/index.php?p=46&more=1&c=1&tb=1&pb=1
"Ian Bell" <itb@yahoo.com> Đ´ČëÓĘźţ

No its not. There is no schematic. Do you actually test your links?

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Kevin Aylward]

Winfield Hill wrote:

Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

T3 would seem to be a problem as well. If its such that it is a current
source, as it nominally looks like, the bias voltage at T4 drain is
dubious. If it can't sink all the current required from T4, it will turn
full on resulting in the 1k alone, in which case it could simply be
removed. If it sinks all the current, then T4 Vds will attempt to go to
zero. Two current sources in series are just as bad as two voltage
sources in ŚŚ. One needs some sort of dc control loop.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Winfield Hill]

Kevin Aylward wrote...

Winfield Hill wrote:
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

T3 would seem to be a problem as well. If its such that it is a current
source, as it nominally looks like, the bias voltage at T4 drain is
dubious. If it can't sink all the current required from T4, it will turn
full on resulting in the 1k alone, in which case it could simply be
removed. If it sinks all the current, then T4 Vds will attempt to go to
zero. Two current sources in series are just as bad as two voltage
sources in ŚŚ. One needs some sort of dc control loop.

Indeed.

Thanks,
- Win

whill_at_picovolt-dot-com

 

[Archer]

"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...

Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need to set

the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and get the
same working current Id.
But in this way, i can't control the gain of the circuit!

And this circuit is designed for low frequency low noise preamp,
I was using multisim to simulate the circuit and I wanna to test the
optimal source impedance to noise figure! I can only find the noise analysis
tools, and get the noise power spectrum in constant source impedance.how can
i get
the curve of source impedance to noise power or figure in a constant
frequency?

 

[Kevin Aylward]

Archer wrote:

"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need to
set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and get
the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at the
fet drains. You cannot put current sources in series like this. One or
the other will turn hard on.

But in this way, i can't control the gain of the circuit!

And this circuit is designed for low frequency low noise preamp,
I was using multisim to simulate the circuit and I wanna to test
the optimal source impedance to noise figure!

Noise figure is pretty much pointless. What you want to know is the
signal/noise ratio. NF is an intermediate calculation that can be
dispensed with.

I can only find the
noise analysis tools, and get the noise power spectrum in constant
source impedance.how can i get
the curve of source impedance to noise power or figure in a constant
frequency?

You probably cant. You should be able to sweep the source resistance
though, well at least you can using a decent simulator like SuperSpice
(http://www.anasoft.co.uk)

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Archer]

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...

Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need to
set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and get
the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at the
fet drains. You cannot put current sources in series like this. One or
the other will turn hard on.

The circuit is to get high resistor and correct working point.
I modified the circuit,showed
here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o_pro
blemofjfet.GIF)
this worked very good. But i don't know how to modify the gain,because the
modification would lead an unbalance that the JFET would not work.
and the source impedance is as smaller as well,how could i making the
matching net
to fit it?

But in this way, i can't control the gain of the circuit!

And this circuit is designed for low frequency low noise preamp,
I was using multisim to simulate the circuit and I wanna to test
the optimal source impedance to noise figure!

Noise figure is pretty much pointless. What you want to know is the
signal/noise ratio. NF is an intermediate calculation that can be
dispensed with.

Here i only get the noise of the circuit,is it a constant for different
sources(with the same sources impedance)?
Would you please give me an example of sweep source resistance with noise
analysis at 10kHz in spice or tell me where to learn sweeping and noise
analysis?

I can only find the
noise analysis tools, and get the noise power spectrum in constant
source impedance.how can i get
the curve of source impedance to noise power or figure in a constant
frequency?

You probably cant. You should be able to sweep the source resistance
though, well at least you can using a decent simulator like SuperSpice
(http://www.anasoft.co.uk)

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Kevin Aylward]

Archer wrote:

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...
Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need
to set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and get
the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at
the fet drains. You cannot put current sources in series like this.
One or the other will turn hard on.


The circuit is to get high resistor and correct working point.
I modified the circuit,showed

here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o

_pro

blemofjfet.GIF)
this worked very good.

It can't. You must have it tuned up by trial and error. What part of
"two current sources in series is a no no" do you not understand? If you
have it arranged so that the drain voltages are, say, mid supply, it
will be like balancing a pencile on its point. A real device will make
the voltage go either way.

As I stated, you *must*, and read my lips *must* have a dc control loop
to stabilise the drain voltages in this type of circuit.

But i don't know how to modify the
gain,because the modification would lead an unbalance that the JFET
would not work. and the source impedance is as smaller as well,how
could i making the matching net
to fit it?

You need to get the DC bias set-up before you can worry about the gain.

But in this way, i can't control the gain of the circuit!

And this circuit is designed for low frequency low noise preamp,
I was using multisim to simulate the circuit and I wanna to test
the optimal source impedance to noise figure!

Noise figure is pretty much pointless. What you want to know is the
signal/noise ratio. NF is an intermediate calculation that can be
dispensed with.


Here i only get the noise of the circuit,is it a constant for
different sources(with the same sources impedance)?

No.

Would you please give me an example of sweep source resistance with
noise analysis at 10kHz in spice or tell me where to learn sweeping
and noise analysis?

You can have a look at the examples in SS, and email me for specific
information.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Kevin Aylward]

Kevin Aylward wrote:

Archer wrote:
"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...
Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need
to set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and
get the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at
the fet drains. You cannot put current sources in series like this.
One or the other will turn hard on.


The circuit is to get high resistor and correct working point.
I modified the circuit,showed


here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o
_pro
blemofjfet.GIF)
this worked very good.

It can't. You must have it tuned up by trial and error. What part of
"two current sources in series is a no no" do you not understand? If
you have it arranged so that the drain voltages are, say, mid supply,
it will be like balancing a pencile on its point. A real device will
make the voltage go either way.

As I stated, you *must*, and read my lips *must* have a dc control
loop to stabilise the drain voltages in this type of circuit.

Although, from inspection it looks like you probably have it as I
described before, the load fets are turned hard on, such that R2 and R3
are the loads, and the fets can be removed.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Archer]

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:t9Zac.1116$Ny4.559@newsfep3-gui.server.ntli.net...

Kevin Aylward wrote:
Archer wrote:
"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...
Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting resistor,
acting as a current-source load for the T2 JFET input amplifier.
T4 is a second-stage FET amplifier with infinite input impedance.
As a result the effective first-stage load resistor is the 510k
to ground. The first-stage gain is 510k/(300 + 1/gm), degraded
somewhat by T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low frequency
signals could saturate the first stage. Therefore, unless you're
sure none are present, any such signals should be aggressively
attenuated (rolled off) by the input coupling capacitor and the
1M input resistor. This means the 2nd-stage coupling capacitor
should be much larger than the input coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i need
to set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and
get the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at
the fet drains. You cannot put current sources in series like this.
One or the other will turn hard on.


The circuit is to get high resistor and correct working point.
I modified the circuit,showed


here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o
_pro
blemofjfet.GIF)
this worked very good.

It can't. You must have it tuned up by trial and error. What part of
"two current sources in series is a no no" do you not understand? If
you have it arranged so that the drain voltages are, say, mid supply,
it will be like balancing a pencile on its point. A real device will
make the voltage go either way.

As I stated, you *must*, and read my lips *must* have a dc control
loop to stabilise the drain voltages in this type of circuit.

Although, from inspection it looks like you probably have it as I
described before, the load fets are turned hard on, such that R2 and R3
are the loads, and the fets can be removed.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.


Thank you for your replies and suggustion of SuperSpice.It is a very good

tools!
But I still have some problem at using SS,when i was making noise analysis
it showed
that the onoise_spectrum is more smaller than inoise_spectrum in an
amplifier.
Is it alright? Or is there some option must be set that i don't know?

And whether the inoise_spectrum include the noise of source impedence? What
does it refers to?

 

[Kevin Aylward]

Archer wrote:

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:t9Zac.1116$Ny4.559@newsfep3-gui.server.ntli.net...
Kevin Aylward wrote:
Archer wrote:
"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...
Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting
resistor, acting as a current-source load for the T2 JFET
input amplifier. T4 is a second-stage FET amplifier with
infinite input impedance. As a result the effective
first-stage load resistor is the 510k to ground. The
first-stage gain is 510k/(300 + 1/gm), degraded somewhat by
T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low
frequency signals could saturate the first stage. Therefore,
unless you're sure none are present, any such signals should
be aggressively attenuated (rolled off) by the input coupling
capacitor and the 1M input resistor. This means the 2nd-stage
coupling capacitor should be much larger than the input
coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i
need to set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and
get the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at
the fet drains. You cannot put current sources in series like
this. One or the other will turn hard on.


The circuit is to get high resistor and correct working point.
I modified the circuit,showed



here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o
_pro
blemofjfet.GIF)
this worked very good.

It can't. You must have it tuned up by trial and error. What part of
"two current sources in series is a no no" do you not understand? If
you have it arranged so that the drain voltages are, say, mid
supply, it will be like balancing a pencile on its point. A real
device will make the voltage go either way.

As I stated, you *must*, and read my lips *must* have a dc control
loop to stabilise the drain voltages in this type of circuit.

Although, from inspection it looks like you probably have it as I
described before, the load fets are turned hard on, such that R2 and
R3 are the loads, and the fets can be removed.

Thank you for your replies and suggustion of SuperSpice.It is a very
good tools!
But I still have some problem at using SS,when i was making noise
analysis it showed
that the onoise_spectrum is more smaller than inoise_spectrum in an
amplifier.

Not usually, but possible, if the gain < 1

Is it alright? Or is there some option must be set that i don't know?

Probably operator error.

And whether the inoise_spectrum include the noise of source
impedence? What does it refers to?

It is the total noise in the circiuit, including the source.

email me a ziped up ypur name.sss schematic file and I can have a look
at it.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Archer]

Unfortunately,It seems that my Email can't be sent to you,because of
blocking.
Do you use a hotmail or yahoo Email?
I pasted the circuit here http://xydarcher.51.net/amp.rar
And this is the messages:


Hello Kevin,
Thank you for your help on news group. This is the circuit file,the
V(ONOISE_Spectrum) is about 800uV/sqrt(Hz) at 10kHz and the
V(INOISE_Spectrum) is about serval mV/Sqrt(Hz).
And is there a easy way to get the gain of the amplifier besides using
AC analysis?When I am using parameter sweep, I can't see all curves
when i choose signals from workspace,is it a bug or error operation?
Archer


"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:bl7cc.4$xE.1@newsfe1-win...

Archer wrote:
"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:t9Zac.1116$Ny4.559@newsfep3-gui.server.ntli.net...
Kevin Aylward wrote:
Archer wrote:
"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:CFOac.1$Ny4.0@newsfep3-gui.server.ntli.net...
Archer wrote:
"Winfield Hill" <Winfield_member@newsguy.com> Đ´ČëÓĘźţ
news:c4eeqd0mr8@drn.newsguy.com...
Archer wrote...

http://xydarcher.51.net/problem%20of%20jfet%20amp.GIF
"What's this section doing?"

T1 is a depletion-mode JFET with a source bias-setting
resistor, acting as a current-source load for the T2 JFET
input amplifier. T4 is a second-stage FET amplifier with
infinite input impedance. As a result the effective
first-stage load resistor is the 510k to ground. The
first-stage gain is 510k/(300 + 1/gm), degraded somewhat by
T2's presumably-high dynamic output resistance.

One caution in using this circuit: At low frequencies the 510k
load is decoupled from T2's drain, which means that low
frequency signals could saturate the first stage. Therefore,
unless you're sure none are present, any such signals should
be aggressively attenuated (rolled off) by the input coupling
capacitor and the 1M input resistor. This means the 2nd-stage
coupling capacitor should be much larger than the input
coupling capacitor.

Thanks,
- Win

whill_at_picovolt-dot-com

In the condition that T1 and T2 is the same type, should i
need to set the T1's bias-setting resistor
the same as T2's? It's to make the two JFETs in working area and
get the same working current Id.

Forget this circuit. It can't work. For this type of current load
design, you will need to have a dc loop to control the voltages at
the fet drains. You cannot put current sources in series like
this. One or the other will turn hard on.


The circuit is to get high resistor and correct working point.
I modified the circuit,showed



here(http://science.blogger.cn/images/science.blogger.cn/xydarcher/195/o
_pro
blemofjfet.GIF)
this worked very good.

It can't. You must have it tuned up by trial and error. What part of
"two current sources in series is a no no" do you not understand? If
you have it arranged so that the drain voltages are, say, mid
supply, it will be like balancing a pencile on its point. A real
device will make the voltage go either way.

As I stated, you *must*, and read my lips *must* have a dc control
loop to stabilise the drain voltages in this type of circuit.

Although, from inspection it looks like you probably have it as I
described before, the load fets are turned hard on, such that R2 and
R3 are the loads, and the fets can be removed.

Thank you for your replies and suggustion of SuperSpice.It is a very
good tools!
But I still have some problem at using SS,when i was making noise
analysis it showed
that the onoise_spectrum is more smaller than inoise_spectrum in an
amplifier.

Not usually, but possible, if the gain < 1

Is it alright? Or is there some option must be set that i don't know?


Probably operator error.

And whether the inoise_spectrum include the noise of source
impedence? What does it refers to?

It is the total noise in the circiuit, including the source.

email me a ziped up ypur name.sss schematic file and I can have a look
at it.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Kevin Aylward]

Archer wrote:

"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:bl7cc.4$xE.1@newsfe1-win...

Thank you for your replies and suggustion of SuperSpice.It is a very
good tools!
But I still have some problem at using SS,when i was making noise
analysis it showed
that the onoise_spectrum is more smaller than inoise_spectrum in an
amplifier.

Not usually, but possible, if the gain < 1

Is it alright? Or is there some option must be set that i don't
know?


Probably operator error.

And whether the inoise_spectrum include the noise of source
impedence? What does it refers to?

It is the total noise in the circiuit, including the source.

email me a ziped up ypur name.sss schematic file and I can have a
Unfortunately,It seems that my Email can't be sent to you,because of
blocking.

Ho hum. Did you actually look at my email address? The return address
has a "dot" instead of a "." and an "EXTRACT" that also must be removed.

I assume that people are aware that return emails are coded, but such
that they can be guessed at. There is also one in my signature below.

Do you use a hotmail or yahoo Email?
I pasted the circuit here http://xydarcher.51.net/amp.rar

I have no idea what this file type is. Its a binary of some sort. I
can't read it.

And this is the messages:


Hello Kevin,
Thank you for your help on news group. This is the circuit file,the
V(ONOISE_Spectrum) is about 800uV/sqrt(Hz) at 10kHz and the
V(INOISE_Spectrum) is about serval mV/Sqrt(Hz).
And is there a easy way to get the gain of the amplifier besides using
AC analysis?

This dosnt make any sense to me. The gain *is* the ac gain, and thats
what an ac analysis will do with an input of 1V.

When I am using parameter sweep, I can't see all curves
when i choose signals from workspace,is it a bug or error operation?
Archer

I don't know why this should occur. Are you sure each run has different
data so that graphs are not overlaid? certainly when I check on my
system, clicking on the signals in the list will display all runs. Try
it on a example, e.g. BipolerOutputCharacteristics.sss

Double click on the graph area, and use the "signals" tab of the dialog
and try manually enabling each signal for each run. Make sure the "run
select" is set to display (each) all runs.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.

 

[Archer]

What about this link?
http://xydarcher.51.net/amp.zip
can you uncompress .zip file?






"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:6iNcc.4$lA5.0@newsfe1-win...

Archer wrote:


"Kevin Aylward" <kevindotaylwardEXTRACT@anasoft.co.uk> Đ´ČëÓĘźţ
news:bl7cc.4$xE.1@newsfe1-win...

Thank you for your replies and suggustion of SuperSpice.It is a very
good tools!
But I still have some problem at using SS,when i was making noise
analysis it showed
that the onoise_spectrum is more smaller than inoise_spectrum in an
amplifier.

Not usually, but possible, if the gain < 1

Is it alright? Or is there some option must be set that i don't
know?


Probably operator error.

And whether the inoise_spectrum include the noise of source
impedence? What does it refers to?

It is the total noise in the circiuit, including the source.

email me a ziped up ypur name.sss schematic file and I can have a
Unfortunately,It seems that my Email can't be sent to you,because of
blocking.

Ho hum. Did you actually look at my email address? The return address
has a "dot" instead of a "." and an "EXTRACT" that also must be removed.

I assume that people are aware that return emails are coded, but such
that they can be guessed at. There is also one in my signature below.

Do you use a hotmail or yahoo Email?
I pasted the circuit here http://xydarcher.51.net/amp.rar

I have no idea what this file type is. Its a binary of some sort. I
can't read it.

And this is the messages:


Hello Kevin,
Thank you for your help on news group. This is the circuit file,the
V(ONOISE_Spectrum) is about 800uV/sqrt(Hz) at 10kHz and the
V(INOISE_Spectrum) is about serval mV/Sqrt(Hz).
And is there a easy way to get the gain of the amplifier besides using
AC analysis?

This dosnt make any sense to me. The gain *is* the ac gain, and thats
what an ac analysis will do with an input of 1V.

When I am using parameter sweep, I can't see all curves
when i choose signals from workspace,is it a bug or error operation?
Archer


I don't know why this should occur. Are you sure each run has different
data so that graphs are not overlaid? certainly when I check on my
system, clicking on the signals in the list will display all runs. Try
it on a example, e.g. BipolerOutputCharacteristics.sss

Double click on the graph area, and use the "signals" tab of the dialog
and try manually enabling each signal for each run. Make sure the "run
select" is set to display (each) all runs.

Kevin Aylward
salesEXTRACT@anasoft.co.uk
http://www.anasoft.co.uk
SuperSpice, a very affordable Mixed-Mode
Windows Simulator with Schematic Capture,
Waveform Display, FFT's and Filter Design.

"quotes with no meaning, are meaningless" - Kevin Aylward.