problem with a state machine

[Simone Winkler]

Hello!

I've got a problem with a state machine that i'm modeling for the
communication with the PDIUSB12-chip for USB communication:
(By the way - do you know if there is already an existing vhdl-code for this
task to download somewhere?)

I did a state machine for writing with 5 states, and in the state
"WRITE_INIT" i need to do a write of 3 bytes (one every clock cycle). But as
I simulate my code with modelsim, it never gets to the 2nd byte, it just
stops. I cannot understand it!

THANK YOU!
Simone

Here is the part of my code:

PROCESS (reset,CLK, next_sreg)
BEGIN
IF CLK='1' AND CLK'event THEN
sreg <= next_sreg;
init_s <= next_init_s;
END IF;
END PROCESS;

write_stm: PROCESS (sreg,isr,RESET,wr_end,write_endp) is

variable init_count: integer range 2 downto 0:=2;
variable data_count: integer range len-1 downto 0;
BEGIN
sel_ep <= '0'; valbuf <= '0'; wr_data <= '0'; wr_init <= '0'; write_out_s
<= X"00";

next_sreg<=IDLE;

IF ( RESET='1' ) THEN
next_sreg<=IDLE;
wr_init<='0';
wr_data<='0';
valbuf<='0';
sel_ep<='0';
write_out_s <= X"00";
next_init_s<=2;
data_count:=len;
ELSE
CASE sreg IS
WHEN IDLE =>
[...]
next_sreg<=SEL_ENDP;
WHEN SEL_ENDP =>
[...]
IF ( isr='0' ) THEN
next_sreg<=WRITE_INIT;
write_out_s <= X"03";
ELSE
next_sreg<=IDLE;
END IF;

------------------------------------------------

WHEN WRITE_INIT =>
wr_data<='0';
valbuf<='0';
sel_ep<='0';
wr_init<='1';
IF (isr='0') THEN
case init_s is
when 2 =>
next_sreg<=WRITE_INIT;
write_out_s <= X"F0";
next_init_s <= 1;
when 1 =>
next_sreg<=WRITE_INIT;
write_out_s <= X"00";
next_init_s <= 0;
when 0 =>
write_out_s <= conv_std_logic_vector(len,8);
next_sreg<=WRITE_DATA;
next_init_s <= 2;
end case;
end if;
IF ( isr='1' ) THEN
next_sreg<=SEL_ENDP;
END IF;

------------------------------------------------

WHEN WRITE_DATA =>
wr_init<='0';
valbuf<='0';
sel_ep<='0';
wr_data<='1';
IF ( wr_end='0' AND isr='0' ) THEN
next_sreg<=WRITE_DATA;
if(data_count>0) then
write_out_s <= write_in;
data_count:=data_count-1;
end if;
END IF;
IF ( isr='0' AND wr_end='1' ) THEN
next_sreg<=VAL_BUF;
data_count:=len;
wr_end <='1';
END IF;
IF ( isr='1' ) THEN
next_sreg<=WRITE_INIT;
END IF;
WHEN VAL_BUF =>
[...]
next_sreg<=IDLE;
write_out_s <= X"FA";
[...]
WHEN OTHERS =>
END CASE;
END IF;
END PROCESS write_stm;

 

[Jim Wu]

PROCESS (reset,CLK, next_sreg)
BEGIN
IF CLK='1' AND CLK'event THEN
sreg <= next_sreg;
init_s <= next_init_s;
END IF;
END PROCESS;

"reset" and "next_sreg" should NOT be in the sensitivity list in the clocked
process above.

Jim Wu
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips