Problem while writing the file

[Shraddhs]

Hello,
I have tried this code on Modelsim, but it is not writing the file
in readable form.
some symbols r there.........
Please help out





library ieee,STD;
USE IEEE.STD_LOGIC_ARITH.ALL;
use ieee.std_logic_1164.ALL;
use ieee.std_logic_unsigned.ALL;
USE STD.TEXTIO.ALL;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
entity mat_add is

end mat_add;

architecture matadd1 of mat_add is
type subchar is('s','t');
type matrix is array(POSITIVE range 1 to 3,NATURAL range 1 to 3)
of integer;
type matrix_out is file of integer;
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
SIGNAL k : integer ;
SIGNAL clock : BIT := '0';
file matout : matrix_out
open WRITE_MODE is "E:\shweta\extra\RCS card\examples\matout.txt";
begin
clock <= not(clock)after 10 ns;
process
VARIABLE i : INTEGER :=1;
VARIABLE j : INTEG

ER :=1;
-- FILE outFile : TEXT IS OUT "matout.txt";
VARIABLE outLine : LINE;
VARIABLE mat1 : matrix;
VARIABLE mat2 :matrix;
begin
for i in 1 to 3 loop
for j in 1 to 3 loop
mat1(i,j) := j+1 ;
mat2(i,j) := mat1(i,j);
end loop;
end loop;
for i in 1 to 3 loop
for j in 1 to 3 loop
-- WRITE(outLine, lineNumber, right, 3);
WAIT UNTIL clock = '1' AND clock'EVENT;
-- WRITE(outLine, HT);
k <= mat2(i,j);
WRITE(matout,k);
end loop;
end loop;
END PROCESS;
end matadd1;

 

[Brian Drummond]

On Wed, 18 Jun 2008 23:23:42 -0700 (PDT), Shraddhs
<shraddhs.vora@gmail.com> wrote:

Hello,
I have tried this code on Modelsim, but it is not writing the file
in readable form.
some symbols r there.........
Please help out

That's because you are writing a binary file.

You could probably convert the data to a textual representation before
writing it by

WRITE(matout,integer'image(k));
but better to read about text file output in any book on VHDL.

- Brian