Problem while updating the output---Help required

K

Kashif

Guest
Hello all

I have problem in the following code while updating the output
(clk_reg) in my second process

I am assigning temp_reg (Signal ) to clk_reg (to final output) but the
output is 0 or UNsigned (U) ... However the signal temp_reg is having
correct output.

Please help me out .....regarding this




Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;


entity Power_reg is
port (
clk, rst : in std_logic;
sys_clk : in std_logic;
core_power_reg : in std_logic_vector(8 downto 0);
core_clock_reg : in std_logic_vector(8 downto 0);
proc_power_bit : in std_logic;
proc_clk_bit : in std_logic;
power_reg : out std_logic_vector(9 downto 0);
clk_reg : out std_logic_vector(9 downto 0)
);
end Power_reg;

--}} End of automatically maintained section

architecture rtl_power_reg of Power_reg is

signal Sys_clk_reg : std_logic_vector (9 downto 0);
signal temp_reg : std_logic_vector(9 downto 0);
signal power_tmp_reg : std_logic_vector(9 downto 0);
signal clk_tmp_reg :std_logic_vector(9 downto 0);

begin


-- Sequential process
process(clk,rst,power_tmp_reg,Sys_clk_reg, temp_reg)
begin
if rst = '0' then
power_reg <= (others => '0');
clk_reg <= (others => '0');

elsif clk'event AND clk='1' then

power_reg <= power_tmp_reg;

end if ;
end process;


-- Combinational Process
process(proc_clk_bit, core_clock_reg, sys_clk, proc_power_bit,
core_power_reg)
begin
-- replicate /copy sys_clk to 10 bit register
Sys_clk_reg <= (sys_clk & sys_clk & sys_clk & sys_clk & sys_clk &
sys_clk & sys_clk & sys_clk & sys_clk & sys_clk);

power_tmp_reg <= proc_power_bit & core_power_reg;

temp_reg <= NOT(proc_clk_bit & core_clock_reg);

clk_tmp_reg(0) <= Sys_clk_reg(0) AND temp_reg(0);
clk_tmp_reg(1) <= Sys_clk_reg(1) AND temp_reg(1);
clk_tmp_reg(2) <= Sys_clk_reg(2) AND temp_reg(2);
clk_tmp_reg(3) <= Sys_clk_reg(3) AND temp_reg(3);
clk_tmp_reg(4) <= Sys_clk_reg(4) AND temp_reg(4);
clk_tmp_reg(5) <= Sys_clk_reg(5) AND temp_reg(5);
clk_tmp_reg(6) <= Sys_clk_reg(6) AND temp_reg(6);
clk_tmp_reg(7) <= Sys_clk_reg(7) AND temp_reg(7);
clk_tmp_reg(8) <= Sys_clk_reg(8) AND temp_reg(8);
clk_tmp_reg(9) <= Sys_clk_reg(9) AND temp_reg(9);
-- Problem with following output
clk_reg <= clk_tmp_reg;
end process;

end rtl_power_reg;
 
Hi!! You are simulating it? With which program?
When you say that:

the output is 0 or UNsigned (U)
Click to expand...
you intend U like Undriven (if you are simulating..) or what else?
 
Hello

I am using ModelSim for simulation. The output is ok when it is 0 but
when it should be one it is X dont care...
however the signal 'clk_tmp_reg' has correct waveform. I am assigning
clk_reg <= clk_tmp_reg to have the output but it is not following the
clk_tmp_reg.

if u need test bench it is below


Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;

entity Power_reg_tb is end;

architecture tb of Power_reg_tb is

component Power_reg
port (
clk, rst : in std_logic;
sys_clk : in std_logic;
core_power_reg : in std_logic_vector(8 downto 0);
core_clock_reg : in std_logic_vector(8 downto 0);
proc_power_bit : in std_logic;
proc_clk_bit : in std_logic;
power_reg : out std_logic_vector(9 downto 0);
clk_reg : out std_logic_vector(9 downto 0)
);
end component;

signal clk, rst : std_logic := '0';
--signal sys_clk : std_logic := '0';
signal core_power_reg : std_logic_vector(8 downto 0) := "000000000";
signal core_clock_reg : std_logic_vector(8 downto 0) := "000000000";
signal proc_power_bit : std_logic := '0';
signal proc_clk_bit : std_logic := '0';
signal pwr_reg : std_logic_vector(9 downto 0);
signal clk_reg : std_logic_vector(9 downto 0);

for U1: Power_reg use entity work.Power_reg(rtl_power_reg);

begin

U1: Power_reg port map ( clk, rst, clk, core_power_reg, core_clock_reg,
proc_power_bit, proc_clk_bit, pwr_reg, clk_reg);

rst <= '1' after 30 ns;
clk <= not(clk) after 10 ns;
--sys_clk <= not(sys_clk) after 20 ns;


process
begin
core_power_reg <= "000000010" after 50 ns,
"001000010" after 100 ns,
"100000010" after 150 ns;

wait for 100 ns;

core_clock_reg <= "000000010" after 50 ns,
"000100010" after 200 ns,
"100000010" after 400 ns;

proc_power_bit <= '1' after 100 ns;

proc_clk_bit <= '1' after 150 ns;


wait;
end process;

end tb;
 
Kashif wrote:
Hello all

I have problem in the following code while updating the output
(clk_reg) in my second process

I am assigning temp_reg (Signal ) to clk_reg (to final output) but the
output is 0 or UNsigned (U) ... However the signal temp_reg is having
correct output.

...
-- Sequential process
process(clk,rst,power_tmp_reg,Sys_clk_reg, temp_reg)
begin
if rst = '0' then
power_reg <= (others => '0');
clk_reg <= (others => '0');
Click to expand...
You assign a '0' to clk_reg permanently here.

-- Combinational Process
process(proc_clk_bit, core_clock_reg, sys_clk, proc_power_bit,
core_power_reg)
begin
-- replicate /copy sys_clk to 10 bit register
...
-- Problem with following output
clk_reg <= clk_tmp_reg;
Click to expand...
You try to assign another signal to clk_reg here.

Think in terms of hardware. Your code has defined two sources for
clk_reg. Therefore, in hardware, you have the outputs of two gates (one
combinational and one a flipflop) driving the same signal. When both are
outputting the same value ('0' in this case), the signal is fine. When
they are outputting different values, the signal is bad ('X').

Never drive the same signal from two processes.
 
Kashif wrote:

I have problem in the following code while updating the output
(clk_reg) in my second process
Click to expand...
You can eliminate this sort of problem
by keeping all the code related to
the same entity port outputs in the
same process.

Here are some examples:
http://home.comcast.net/~mike_treseler/

-- Mike Treseler
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top