Problem when output data with some interval

Hi, my friends,

I have a problem when I try to output a data from ROM every 20 clocks.
The code works fine in behavioral level simulation but not correct in
Post-Route simulation.

Please help me!


library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity testDriver is
generic(
M_COUNTER : integer := 20;
M_DATASIZE : integer := 4 -- test bench ROM size
);
port( clk_in: in std_logic; -- system clock
en_in: in std_logic:= '1' ; -- enable signal
en_clr_in: in std_logic:= '0'; -- reset signal

clk_out: out std_logic; -- output system clock
en_out: out std_logic ; -- clock enable signal. Set it to '1'
en_clr_out: out std_logic ; -- reset signal. Set it to '0'
bin_data_out: out std_logic; -- Data from ROM
init_en_out: out std_logic; -- Set it to '1'
const_out: out std_logic -- Set it to '0'
);
end testDriver;

----------------------------------------------------

architecture behv_testDriver of testDriver is


--ROM. Save test data.
type ROM250by1 is array (0 to M_DATASIZE-1) of std_logic; --
totally 250
constant rom_data: ROM250by1 := ('1','0','1','0');

-- index of data in the ROM
signal nIndexBuf : integer := 0;

-- counter
signal nCounterBuf: integer := 0;

-- temp signal for input
signal clk_tmp : std_logic ;
signal en_tmp : std_logic ;
signal en_clr_tmp : std_logic;
signal out_tmp : std_logic := '0';

-- use as counter clear signal, index clear signal
signal clr_257 : std_logic := '0' ;
begin
clk_tmp <= clk_in;
en_tmp <= en_in;
en_clr_tmp <= en_clr_in;
out_tmp <= rom_data(nIndexBuf);

clk_out <= clk_tmp;
en_out <= en_tmp;
en_clr_out <= en_clr_tmp;

bin_data_out <= out_tmp;
const_out <= '1' ;

coun257_gen: process(clk_tmp)
begin

if clk_tmp'event and clk_tmp = '1' then
if (en_tmp = '1') then
if (en_clr_tmp = '1' or clr_257 = '1') then
nCounterBuf <= 0;
else
nCounterBuf <= nCounterBuf + 1;
end if; -- clear
end if; -- enable
end if; -- clock
end process;

clr257_gen: process(en_clr_tmp,nCounterBuf)
begin

if (en_clr_tmp = '1') then
clr_257 <= '1';
elsif nCounterBuf = M_COUNTER - 1 then
clr_257 <= '1';
else
clr_257 <= '0';
end if; -- clock
end process;

data_output: process(nCounterBuf, en_clr_tmp)
begin
if (en_clr_tmp = '1')then
nIndexBuf <= 0 ;
else
nIndexBuf <= (nIndexBuf+1) mod M_DATASIZE;
end if; -- clock
end process;

init_en_out <= '0';

end behv_testDriver;

 

[KJ]

On Mar 14, 11:21 am, ppk.mym...@gmail.com wrote:

I have a problem when I try to output a data from ROM every 20 clocks.
The code works fine in behavioral level simulation but not correct in
Post-Route simulation.
Anything in particular not working or do you expect people to do all

the work?

<snip>
The following process will not work in a real device and possibly in
post-route simulation either so it might be the cause of your
problems. The problem is that signal nIndexBuf which comes out of
this process is a combinatorial loop (i.e. there is a feedback path in
the logic with no intervening flip flop). The loop is closed by the
"nIndexBuf <= (nIndexBuf+1) mod M_DATASIZE;" statement. If you peruse
your fitter report you should probably see a warning somewhere
indicating this as well....heed the warnings, they are generally
design errors.

data_output: process(nCounterBuf, en_clr_tmp)
begin
if (en_clr_tmp = '1')then
nIndexBuf <= 0 ;
else
nIndexBuf <= (nIndexBuf+1) mod M_DATASIZE;
end if; -- clock
end process;

To fix it you need to change the 'data_output' process to a clocked
process.

Also get rid of your 'clk_tmp' signal, you should be using 'clk_in'
instead on all clocked processes.

Lastly, I don't know how you're using the 'clk_out' signal in the rest
of your design, but don't expect that this will occur prior to the
outputs changing automatically without some effort on your part to
control for this. There could very well be more skew on the path to
'clk_out' than there is clock to output delay on the other signals.
This can be managed and designed correctly to happen, and it may not
be a problem in your particular case, just something to keep in mind.

Kevin Jennings