Problem using same instance multiple times in Verilog

We are facing some problem with Multiple Module Instantiation in
Verilog. We are using ModelSim Editor for developing the simulation.
There isn't any compiler error. It is only when we are trying to load
the design that the tool is throwing an error of the form



# ERROR: /TestBench.V(111): Instantiation of 'PC' failed (design unit
not found).
# Region: /test_benchr
# Searched libraries:
# Datapath



PC is an instance of a module, which is being used multiple times.

 

[Ajeetha]

Sounds to me like you have not compiled the file that contains the
definition of module which you have instantiated as PC.

Show us clearly your compile steps. In simple case I would do:

vlib work
vlog my_p_module.v
vlog TestBench.V
vsim test_benchr

HTH
Ajeetha, CVC
www.noveldv.com