problem using $fdisplay to dump signals into file

[dinesh]

Hi all,

I have encountered the following senario while running a simulation(A
very big testcase indeed). Iam using th NC-Verilog Simulator.

Scenario: I am monitoring a signal. When it is asserted i am calling
"$finish" to stop the simulation. I am using "$fdisplay" to dump the
values into the log file.

Problem: I observed that the values of signals were not dumped into
the logfile eventhough they are available at waveform (in signal scan).

If i increase the simulation time (by adding some
delay before calling $finish) then the values were dumped into log
file.

Let me know why and how much delay should we add to dump
the values properly in to the file.


Note : The test case is big one.

--Dinesh

 

How are you triggering the $fdisplay? If you are using an always block
that executes the $fdisplay, I would guess that you have a race
condition between the code that calls $finish and the execution of the
always block. If they happen in the exact same simulation time, then
there is no guarantee that the always block will execute and call
$fdisplay before the other block calls $finish. In fact, if the $finish
is in the same initial block that is changing the inputs to your
design, the initial block will generally continue and execute the
$finish before any of the fanout of those inputs is evaluated. In this
case, any non-zero delay before the $finish will solve your problem.

Or perhaps you are running into an issue with output buffering, though
the buffers should get flushed when you actually exit the simulator.
Unless you are trying to look at the output before the simulator exits,
I wouldn't expect any problems there.

 

Reading your description again, I see that you are triggering the
$finish based on a signal. So this may be a race between that signal
triggering the block with the $finish, and other signals triggering the
block with the $fdisplay. Again, any non-zero delay before the $finish
should resolve the race.