Problem using EDK tutorial for Memec board with Synplicity.

B

Brijesh

Guest
Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis tool.
The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp".
I guess the last _xst is for XST specific. Do I just rename the file? or
how do I move ahead with the tutorial using Synplicity for my synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
 
Was going through the Documentation. Buried deep within I found this

"Currently, Platform Generator only supports XST (Xilinx Synthesis
Technology)."

Guess Iam stuck. Unless there is a tutorial that does not use the
Platform Generator. Is there a way to change the Synthesis tool option
once the project is generated using the Platform Generator.

Or more basic question does EDK support Synplicity at all?

Thanks
brijesh


Brijesh wrote:

Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis tool.
The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp".
I guess the last _xst is for XST specific. Do I just rename the file? or
how do I move ahead with the tutorial using Synplicity for my synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
Click to expand...
 
For user IPs, there are multiple ways you can
achieve this as part of XPS flow.

1. Pre-synthesize the IP using 3rd party synthesis tool
and import it as a black-box module (use MPD+BBD) in EDK.

2. User Export-To-ProjNav flow. Do not synthesize the IP.
XPS will add the HDL files related to the IP to your projnav
project. You can synthesize 3rd party synthesis tool in
ProjNav, run ISE implementation tools and import back
the bitstream

3. Use XPS's user makefile feature. Do not synthesize the
IP, but mark it as IMP_NETILST=FALSE. PlatGen will create
a wrapper HDL for user IP, but will not synthesize it.
In XPS--> Project Options, specify a user make file to be
used -- say mymakefile.make. Copy XPS generated system.make
into mymakefile.make. Create a file, say mysynthesis.sh.
Make a call to the batch mode of your favorite synthesis
tool to synthesize user IP. In the target where XPS calls
synthesis.sh, replace it with mysynthesis.sh.

4. Send email to hotline@xilinx.com for assistance

Brijesh wrote:
Was going through the Documentation. Buried deep within I found this

"Currently, Platform Generator only supports XST (Xilinx Synthesis
Technology)."

Guess Iam stuck. Unless there is a tutorial that does not use the
Platform Generator. Is there a way to change the Synthesis tool option
once the project is generated using the Platform Generator.

Or more basic question does EDK support Synplicity at all?

Thanks
brijesh


Brijesh wrote:

Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis
tool. The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file
"system_dcm_wrapper_xst.srp". I guess the last _xst is for XST
specific. Do I just rename the file? or how do I move ahead with the
tutorial using Synplicity for my synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
Click to expand...

--
/ 7\'7 Paulo Dutra (paulo.dutra@xilinx.com)
\ \ ` Xilinx hotline@xilinx.com
/ / 2100 Logic Drive http://www.xilinx.com
\_\/.\ San Jose, California 95124-3450 USA
 
Look up "syn_edif_bit_format" in the Synplicity help file. It will
tell you how to match the <> in your UCF files.

There is also a Xilinx program that will generate the interface files
needed by EDK. Basically, EDK needs an extra file describing the
ports and generics of a "peripheral". This file is generated from
the top level verilog module or VHDL entity of your peripheral.
I don't remember the name of the program, but I will ask around.

- Ken McElvain


Brijesh wrote:

Was going through the Documentation. Buried deep within I found this

"Currently, Platform Generator only supports XST (Xilinx Synthesis
Technology)."

Guess Iam stuck. Unless there is a tutorial that does not use the
Platform Generator. Is there a way to change the Synthesis tool option
once the project is generated using the Platform Generator.

Or more basic question does EDK support Synplicity at all?

Thanks
brijesh


Brijesh wrote:

Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis
tool. The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file
"system_dcm_wrapper_xst.srp". I guess the last _xst is for XST
specific. Do I just rename the file? or how do I move ahead with the
tutorial using Synplicity for my synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
Click to expand...
 
Paulo and Ken,
Thanks for the reply.

This was first time I even fired up the EDK application. To keep things
simple I installed evaluation version of the XST and finished the tutorial.
I will look into your suggested flow, once I get comfortable with the
design flow and figure out some more things.

This is for information if anybody else if trying out the tutorial.
I did observe one more thing, the P&R reported had 4 errors.

--------------------------------------------------------------------------------
* PERIOD analysis for net "system_dcm/syste | 10.000ns | 13.255ns |0
m_dcm/CLK0_BUF" derived from NET "bufgp_ | | |

83/IBUFG" PERIOD = 10 nS HIGH 50.00000 | | |

0 % | | |

--------------------------------------------------------------------------------
* PERIOD analysis for net "system_dcm/syste | 3.333ns | 4.282ns |0
m_dcm/CLKFX_BUF" derived from NET "bufgp | | |

_83/IBUFG" PERIOD = 10 nS HIGH 50.0000 | | |

00 % | | |

--------------------------------------------------------------------------------

I just went ahead and tried it out inspite of this one. It seemed to
work, I did get required output on the terminal screen.

Thanks again.

Brijesh wrote:

Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis tool.
The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp".
I guess the last _xst is for XST specific. Do I just rename the file? or
how do I move ahead with the tutorial using Synplicity for my synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
Click to expand...
 
Brijesh,

Although Plat Gen only supports XST, that's not a problem for you. EDK will
synthesise the processor part of the design using XST (despite the fact that
you have ISE without XST). EDK still has access to XST even if you
don't....

All you need to do then is take your HDL, create black boxes (for the
processor cores & peripherals) inside the design, Synthesise as normal using
Synplify, then let ISE tie everything together for you.

So in answer to your last question - yes, you can still use Synplify just
slightly further into the loop.

Best Regards,

--
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information

"Brijesh" <brijesh_xyz@cfrsi.com> wrote in message
news:c54fmf$pkv$1@solaris.cc.vt.edu...
Was going through the Documentation. Buried deep within I found this

"Currently, Platform Generator only supports XST (Xilinx Synthesis
Technology)."

Guess Iam stuck. Unless there is a tutorial that does not use the
Platform Generator. Is there a way to change the Synthesis tool option
once the project is generated using the Platform Generator.

Or more basic question does EDK support Synplicity at all?

Thanks
brijesh


Brijesh wrote:

Hi,

My set up is
EDK 6.1
ISE 6.1 (no XST)
Synplicity
Memic VitexII Pro Dev board P4 FG 456

The tutorial expects you to use Xilinx synthesis tool XST. During
initial XPS wizard didnt give me an option to choose the synthesis tool.
The Drop down menu had only one option "None".

I went ahead with the steps and managed to export the project to ISE
project Navigator. Had to manually add the system.vhd and other files.
Then I had the following problems.

1) The bus format in the UCF files had to be changed from <> to ().
2) Got stuck with this error messages

ERROR:NgdBuild:704 - The BRAM instance
'opb_bram_if_cntlr_1_bram/opb_bram_if_cntlr_1_bram/ramb16_s4_s4_0'
could not be found in the netlist. Please verify the instance name in
the BMM file and the netlist.

ERROR:NgdBuild:604 - logical block 'system_dcm' with type
'system_dcm_wrapper' could not be resolved. A pin name misspelling can
cause this, a missing edif or ngc file, or the misspelling of a type
name. Symbol 'system_dcm_wrapper' is not supported in target 'virtex2p'.

The "synthesis" folder does have the file "system_dcm_wrapper_xst.srp".
I guess the last _xst is for XST specific. Do I just rename the file? or
how do I move ahead with the tutorial using Synplicity for my
synthesis.

Any clues on how to proceed would be appreciated.
Thanks
brijesh
Click to expand...
 
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