S
spectrallypure
Guest
Hello all! Has somebody experienced this while simulating a chip
including an ESD power clamp and the package parasitics? The problem
is as follows...
I am experiencing difficulties interpreting the results of a Spectre
simulation of a simple circuit including an binary trasmitter composed
of little logic and an output buffer. In my circuit I am also
considering 2 ESD protections elements: a grounded-gate NMOS
protecting the buffer's output and a power clamp between the vdd and
gnd buses. Furthermore, in order to model the switching noise due to
the buffer's commutation, I am also including a Lp = 5nH inductance in
series with each pin to model the parasitics of the package and the
bondwire.
The problem is that the clamp (which under normal operation behaves as
a 300fF capacitive load between vdd and gnd) resonates with the
parasitics inductances, in the following LC loop:
(offchip)Power_supply_positive_terminal - Lp - (onchip)Vdd_bus - Power
clamp - (onchip)gnd_bus - Lp -
(offchip)Power_supply_negative_terminal. Since this loop lacks of
appreciable resistance, the oscillations are almost not damped at all
and produce big oscillations in the vdd and gnd buses internal to the
chip.
Since I believe the aforementioned LC loop is present in *every* real
chip (which for sure must have a clamp and package inductances in the
power supply loop, but doesn't shows underdamped oscillations on the
power lines), I suspect these results are incorrect and that I am
missing something very important while performing the simulation. I
first though it might have something to do with the model of the
clamp, but I am using the schematic view provided in the vendor's
design kit (Austriamicrosystems 0.35 CMOS), which seems to be a
perfectly fine back-end view, provided for the very purpose in which I
am using it: to perform schematic simulations taking into account its
loading to the circuit. When I perform an AC sweep of the clamp alone,
it does behave like a capacitive load. I don't know what am I
missing...
Thanks in advance for any help/ideals/comments! For a graphical
explanation of this problem, please see:
http://www.edaboard.com/viewtopic.php?p=1046561#1046561
Regards,
Jorge.
including an ESD power clamp and the package parasitics? The problem
is as follows...
I am experiencing difficulties interpreting the results of a Spectre
simulation of a simple circuit including an binary trasmitter composed
of little logic and an output buffer. In my circuit I am also
considering 2 ESD protections elements: a grounded-gate NMOS
protecting the buffer's output and a power clamp between the vdd and
gnd buses. Furthermore, in order to model the switching noise due to
the buffer's commutation, I am also including a Lp = 5nH inductance in
series with each pin to model the parasitics of the package and the
bondwire.
The problem is that the clamp (which under normal operation behaves as
a 300fF capacitive load between vdd and gnd) resonates with the
parasitics inductances, in the following LC loop:
(offchip)Power_supply_positive_terminal - Lp - (onchip)Vdd_bus - Power
clamp - (onchip)gnd_bus - Lp -
(offchip)Power_supply_negative_terminal. Since this loop lacks of
appreciable resistance, the oscillations are almost not damped at all
and produce big oscillations in the vdd and gnd buses internal to the
chip.
Since I believe the aforementioned LC loop is present in *every* real
chip (which for sure must have a clamp and package inductances in the
power supply loop, but doesn't shows underdamped oscillations on the
power lines), I suspect these results are incorrect and that I am
missing something very important while performing the simulation. I
first though it might have something to do with the model of the
clamp, but I am using the schematic view provided in the vendor's
design kit (Austriamicrosystems 0.35 CMOS), which seems to be a
perfectly fine back-end view, provided for the very purpose in which I
am using it: to perform schematic simulations taking into account its
loading to the circuit. When I perform an AC sweep of the clamp alone,
it does behave like a capacitive load. I don't know what am I
missing...
Thanks in advance for any help/ideals/comments! For a graphical
explanation of this problem, please see:
http://www.edaboard.com/viewtopic.php?p=1046561#1046561
Regards,
Jorge.