problem simulating in modelsim gui

[Okashii]

I have this package
PACKAGE my_pkg is
type global_array1 is array(0 to 20) of integer;
END my_pkg;

and an entity
ENTITY synthetic2 IS
port(
returnVar_synthetic2 : OUT integer ;
parameter_a: INOUT global_array1;
CLOCK : IN std_logic ;
RESET : IN std_logic ;
.......

Both of these are on the same file. The syntax checking shows no problem,
but when I run a test bench waveform of a synthetic2 in
modelsim, it says

# ** Error: forloopwave.vhw(36): Unknown identifier 'global_array1base'.

ARCHITECTURE testbench_arch OF forloopwave IS
COMPONENT synthetic2
PORT (
returnVar_synthetic2 : Out INTEGER;
parameter_a : InOut global_array1Base (0 To 20);
.......................

It seems that the type for parameter_a, which was global_array1 defined in
the package, has now changed to 'global_array1base' and is unrecognizable.
Is this any way around this problem?

Any help is appreciated!

 

[Mike Treseler]

Okashii wrote:

I have this package
PACKAGE my_pkg is
type global_array1 is array(0 to 20) of integer;
END my_pkg;

and an entity
ENTITY synthetic2 IS

how about a "use work.my_pkg.all"

above the entity?

-- Mike Treseler

 

[Okashii]

Hi, I did specify
library work;
use work.my_pkg.all;
just above the entity, but the problem still occurs

Also I have another problem:

PACKAGE my_pkg is
subtype myInt is integer range 0 to 20;
END my_pkg;

library work;
use work.my_pkg.all;

ENTITY synthetic2 IS
port(
returnVar_synthetic2 : OUT integer ;
--parameter_a: INOUT global_array1;
parameter_b: INOUT myInt;
....

When I run the testbench waveform, the following error occurs:
# ** Error: forloopwave.vhw(36): Index constraint cannot be applied to
non-array type integer.

The testbench source code says:
ARCHITECTURE testbench_arch OF forloopwave IS
COMPONENT synthetic2
PORT (
returnVar_synthetic2 : Out INTEGER;
parameter_b : InOut INTEGER (0 To 20);

Now the modelsim has turned the parameter_b type to an array!
Is it me or is there sth wrong with modelsim?


----- Original Message -----
From: "Mike Treseler" <mike_treseler@comcast.net>
Newsgroups: comp.lang.vhdl
Sent: Tuesday, October 11, 2005 4:07 PM
Subject: Re: problem simulating in modelsim gui

Okashii wrote:
I have this package
PACKAGE my_pkg is
type global_array1 is array(0 to 20) of integer;
END my_pkg;

and an entity
ENTITY synthetic2 IS


how about a "use work.my_pkg.all"

above the entity?

-- Mike Treseler

 

[sudhi]

Is there a reason why you want to define

parameter_b: INOUT myInt; in the entity declaration and

parameter_b : InOut INTEGER (0 To 20); in the component declaration?

Why not use the same declaration?

 

[Okashii]

Hi, the 2nd line of code is actually generated by the modelsim gui testbench
waveform to simulate the component, however it turn the first line of code,
which is supposed to be a integer range, into an integer array. I assume
that its a bug in modelsim... right now I have to manually go to the .vhw
file to correct the mistake before I simulate the testbench in modelsim. I
also found that if I try to specify a integer array as a port, it will try
to do this initialization during the testbench:

myintarray := "00000000" --assume myintarray has width 8;
Similarly, it misrecognize the user defined type as a bit vector, and I have

to manually change the .vhw file.

"sudhi" <sudhi.kadri@gmail.com> wrote in message
news:1129537448.963317.240100@g14g2000cwa.googlegroups.com...

Is there a reason why you want to define

parameter_b: INOUT myInt; in the entity declaration and

parameter_b : InOut INTEGER (0 To 20); in the component declaration?

Why not use the same declaration?