problem running icarus verilog 0.7 - "target_design entry po

[malexgreen]

Using Mac OSX 10.3 and the precompiled binary for Mac OSX for 10.3.

Here's the command line I use:

iverilog -g1 -B /Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl
-C ~/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/iverilog.conf -v
-tvvp -odes.vvp des.v

Here's the output I get (not des.v is the example code from the
iverilog tar file I downloaded)

What could be causing the error?

Icarus Verilog version 0.7
Copyright 1998-2002 Stephen Williams
$Name: v0_7 $
translate: /Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/ivlpp
-v -L -D__ICARUS__=1 -f/tmp/ivrlg62c0417 |
/Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/ivl -v
-C/tmp/ivrlh62c0417 -g1 -tdll
-fDLL=/Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/vvp.tgt
-fVVP_EXECUTABLE=/Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/../../bin/vvp
-Fcprop -Fnodangle -odes.vvp -- -
Icarus Verilog Preprocessor version $Name: v0_7 $ $State: Exp $
Copyright (c) 1999 Stephen Williams (steve@icarus.com)
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.

This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA
Using language generation: IEEE1364-1995
PARSING INPUT
LOCATING TOP-LEVEL MODULES
top
... done, 0.06 seconds.
ELABORATING DESIGN
... done, 0.56 seconds.
RUNNING FUNCTORS
-F cprop ...
-F nodangle ...
... 1 iterations deleted 4882 dangling signals and 127 events.
(count=4882)
... 2 iterations deleted 4882 dangling signals and 127 events.
(count=0)
... done, 0.06 seconds.
CODE GENERATION -t dll
/Users/magreen/Downloads/iverilog-0.7-macosx10.2-bin/lib/ivl/vvp.tgt:
error: target_design entry point is missing.
error: Code generation had errors.
[ginger:~/Downloads/verilog-0.7/examples] magreen%