problem reading from file using read_memh

[rekz]

I have a test_data.txt which has 276 lines of numbers in hex and I
want to be able to read it and initialize the Memory array using
readmemh.
So I did the following code and tried to pull out the values from the
Memory and only the first value, which is Memory[0] is there and the
rest is 0. How is this possible?
I made sure that my test_data.txt is formatted correctly. The Memory
has the same size as the number of lines in the test_data.txt, so it
should be fine.
Why is this?


module DataMemory(Address, WriteData, MemRead, MemWrite, Clk,
ReadData);
input[31:0] Address; //32-bit address to memory
input[31:0]WriteData; //Data to be written into WriteRegister
input MemRead; //Data in memory location Adress is read if this
control is set
input Clk;
input MemWrite; //WriteData is written in Address during positive

reg [31:0] ReadData;
output[31:0] ReadData;

reg[31:0] Memory [0:275];

//assign ReadData = (MemRead == 1) ? Memory[Address] : 32'h00000000;

always @(posedge Clk) //Memory write
begin

if (MemWrite==1)
Memory[Address] = WriteData;
end

always @(Address or MemRead)
begin
if (MemRead == 1)
ReadData <= Memory[Address]; //Memory read
else
ReadData <= 32'h00000000;
end

initial begin
$readmemh("test_data.txt", Memory);
end


endmodule

 

[Rob]

rekz wrote:

I have a test_data.txt which has 276 lines of numbers in hex and I
want to be able to read it and initialize the Memory array using
readmemh.
So I did the following code and tried to pull out the values from the
Memory and only the first value, which is Memory[0] is there and the
rest is 0. How is this possible?
I made sure that my test_data.txt is formatted correctly. The Memory
has the same size as the number of lines in the test_data.txt, so it
should be fine.
Why is this?


module DataMemory(Address, WriteData, MemRead, MemWrite, Clk,
ReadData);
input[31:0] Address; //32-bit address to memory
input[31:0]WriteData; //Data to be written into WriteRegister
input MemRead; //Data in memory location Adress is read if this
control is set
input Clk;
input MemWrite; //WriteData is written in Address during positive

reg [31:0] ReadData;
output[31:0] ReadData;

reg[31:0] Memory [0:275];

//assign ReadData = (MemRead == 1) ? Memory[Address] : 32'h00000000;

always @(posedge Clk) //Memory write
begin

if (MemWrite==1)
Memory[Address] = WriteData;
end

always @(Address or MemRead)
begin
if (MemRead == 1)
ReadData <= Memory[Address]; //Memory read
else
ReadData <= 32'h00000000;
end

initial begin
$readmemh("test_data.txt", Memory);
end


endmodule

Try changing this line:

reg[31:0] Memory [0:275];

To:

reg[31:0] Memory [275:0];

 

[Chris Briggs]

I suspect the $readmemh is not your problem. If you want to check it
by itself, dump the memory contents after reading.

integer i;
initial begin
$readmemh("test_data.txt", Memory);
for (i = 0; i < 276; i = i + 1)
$display("Memory[%0d] = %h", i, Memory);
end

Assuming that shows all the data, you need to look at the inputs to
this block. What are they doing? Is Address changing multiple times in
one cycle? Is MemRead deasserting after the first read? Does the
result change if you use @* instead of @(Address or MemRead)?

Also, and this is probably nothing, but I've never seen an output
declared as an output after being declared as a reg. Usually it's the
other way around:

output [31:0] ReadData;
reg [31:0] ReadData;

Or, since Verilog-2001:

output reg [31:0] ReadData;

-cb