Problem of Initial Value in VHDL code

I have written a code notes down the position of a particular element
of one array by comparing it with other array.
The program is running fine, with only problem that a value of 7 is
coming Initially in the waveform.
Can someone point what is that thing which is giving this initial 7 in
the output. (STAMP_var1 is the signal to be observer)

I have given the basic program below.
I am also posting code for 2 ROM's and Top level which connects all
of them which will ease you analyzing everything.
Just add the vhdls in a project and see the waveforms.

Thanks in advance.
--------------------------------------------------------------------------------------
---- Basic program
--This is the program I am writting for position stamp

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
package CONV is
constant N : integer := 8 ; -- number of elements to sort
constant M : integer := 4 ; -- size of word to sort
type TYPE_IO is array(0 to N-1) of std_logic_vector(M-1 downto 0);

end CONV;
package body CONV is
end CONV;

--------------------------------------------------------
library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity numberINsorting is

port( in_ved: in std_logic_vector(M-1 downto 0);
in_jala: in std_logic_vector(M-1 downto 0);
clock,Reset: in std_logic;
STAMP_var : out integer:=0;
Z: out TYPE_IO);

end numberINsorting;

architecture BEHVnumberINsorting of numberINsorting is

signal ved: TYPE_IO ;
signal jala: TYPE_IO ;

begin

process(clock,Reset)

variable tmp : std_logic_vector(M-1 downto 0);
variable list : TYPE_IO ;
variable count : integer range 0 to (N-1) ;
------------------------------------------------
variable STS : Boolean;

variable var_temp : integer range 0 to N-1:=0;

constant A : integer :=24;
constant B_COUNT : integer :=32;
constant C : integer :=14;
-----------------------------------------------
begin
----------------------------------------------
--sig_temp <= 0;
if reset='1' then
count:=0;
STS := FALSE;

var_temp := 0;

else if rising_edge(clock) then


if count=(N-1) then ---changes when frame size is
increased count:=0;
else
count:=count +1;
end if;

ved(count)<= in_ved;
jala(count) <= in_jala;


-----------------------------
for i in 0 to N-1 loop

STS := ( ved(i) = jala(N-1) ) ; -- should assign the value TRUE to STS

if STS = TRUE then
var_temp := (i) ; --- assigned the position stamp to variable
end if ;
end loop ;

STAMP_var <= var_temp ;
end if; --end reset
------------------------------

end if; -- end clock

end process;
-----------------------------------------------
end BEHVnumberINsorting;

-------------------------------------------------------------------------
-------------------------------------------------------------------------

--ROM ved


library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity romVED is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romVEDarch of romVED is
begin

process(ADDRESS)
begin
case (ADDRESS) is
when 0 => Q_rom <= "1111"; -- F
when 1 => Q_rom <= "0000"; -- 0
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0001"; -- 1
when 4 => Q_rom <= "1100"; -- C
when 5 => Q_rom <= "1101"; -- D
when 6 => Q_rom <= "0101"; -- 5
when 7 => Q_rom <= "1000"; -- 8


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;

-------------------------------------------------------------------------------
-------------------------------------------------------------------------------

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity romJALA is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romJALAarch of romJALA is
begin

process(ADDRESS)
begin
case (ADDRESS) is

when 0 => Q_rom <= "1100"; -- C
when 1 => Q_rom <= "1101"; -- D
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0101"; -- 5
when 4 => Q_rom <= "1000"; -- 8
when 5 => Q_rom <= "1111"; -- F
when 6 => Q_rom <= "0001"; -- 1
when 7 => Q_rom <= "0000"; -- 0


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;

--------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------
--TOP LEVEL

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;


entity numberstamp_TB is
port(
CLOCK : in STD_LOGIC;
STAMP_var1 : out integer;
Reset : in STD_LOGIC
);
end numberstamp_TB;

architecture archnumberstamp_TB of numberstamp_TB is

---- Component declarations -----

component counterForROM
port (
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out INTEGER range 0 to N-1
);
end component;
component numberINsorting
port (
Reset : in STD_LOGIC;
clock : in STD_LOGIC;
in_jala : in STD_LOGIC_VECTOR(M-1 downto 0);
in_ved : in STD_LOGIC_VECTOR(M-1 downto 0);
STAMP_var : out integer;
Z : out TYPE_IO
);
end component;
component romJALA
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;
component romVED
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;

---- Signal declarations used on the diagram ----

signal NET169 : INTEGER range 0 to N-1;
signal BUS56 : STD_LOGIC_VECTOR (M-1 downto 0);
signal BUS67 : STD_LOGIC_VECTOR (M-1 downto 0);

begin

---- Component instantiations ----

U1 : numberINsorting
port map(
Reset => Reset,
clock => CLOCK,
in_jala => BUS67( M-1 downto 0 ),
in_ved => BUS56( M-1 downto 0 ),
STAMP_var => STAMP_var1
);

U2 : romJALA
port map(
ADDRESS => NET169,
Q_rom => BUS67( M-1 downto 0 )
);

U3 : romVED
port map(
ADDRESS => NET169,
Q_rom => BUS56( M-1 downto 0 )
);

U4 : counterForROM
port map(
CLK => CLOCK,
CLR => Reset,
Q => NET169
);


end archnumberstamp_TB;

 

[Duane Clark]

vedpsingh@gmail.com wrote:

I have written a code notes down the position of a particular element
of one array by comparing it with other array.
The program is running fine, with only problem that a value of 7 is
coming Initially in the waveform.
Can someone point what is that thing which is giving this initial 7 in
the output. (STAMP_var1 is the signal to be observer)
...
else if rising_edge(clock) then
-----------------------------
for i in 0 to N-1 loop
STS := ( ved(i) = jala(N-1) ) ; -- should assign the value TRUE to STS

if STS = TRUE then
var_temp := (i) ; --- assigned the position stamp to variable
end if ;
end loop ;
STAMP_var <= var_temp ;

I'm not sure what you are expecting, since you pretty much showed the
code that matters. Are you expecting the loop to go through a single
iteration on every clock? (that is the only thing I can guess). If so,
that is not the way loops work. The loop executes all 8 iterations on
every clock, so STAMP_var gets set to 7.

 

Thanks Duane.
Your comment helped me to sought out the problem.

I am again posting the whole code with previous problem rectified, but
with a new problem.

If you Guru's simulate all the files which I have provided, you will
find that the OUTPUT "matrix_output" (BASIC PROGRAM below) is
having a value 0080808080808080 latched since beginning, and these
latched values does not get removed.
Please point out the problem.

Thanks in advance.


--TOP LEVEL


library IEEE;
use IEEE.std_logic_1164.all;


entity numberINsorting_TB is
port(
CLOCK : in STD_LOGIC;
Reset : in STD_LOGIC
);
end numberINsorting_TB;

architecture numberINsorting_TB of numberINsorting_TB is

---- Component declarations -----

component counterForROM
port (
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out INTEGER range 0 to N-1
);
end component;
component numberINsorting
port (
Reset : in STD_LOGIC;
clock : in STD_LOGIC;
in_jala : in STD_LOGIC_VECTOR(M-1 downto 0);
in_ved : in STD_LOGIC_VECTOR(M-1 downto 0);
Z : out TYPE_IO
);
end component;
component romJALA
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;
component romVED
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;

---- Signal declarations used on the diagram ----

signal NET169 : INTEGER range 0 to N-1;
signal BUS56 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS67 : STD_LOGIC_VECTOR (7 downto 0);

begin

---- Component instantiations ----

U1 : numberINsorting
port map(
Reset => Reset,
clock => CLOCK,
in_jala => BUS67( 7 downto 0 ),
in_ved => BUS56( 7 downto 0 )
);

U2 : romJALA
port map(
ADDRESS => NET169,
Q_rom => BUS67( 7 downto 0 )
);

U3 : romVED
port map(
ADDRESS => NET169,
Q_rom => BUS56( 7 downto 0 )
);

U4 : counterForROM
port map(
CLK => CLOCK,
CLR => Reset,
Q => NET169
);


end numberINsorting_TB;





---- Basic program

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity numberINsorting is

port( in_ved: in std_logic_vector(M-1 downto 0);
in_jala: in std_logic_vector(M-1 downto 0);
clock,Reset,clock9x: in std_logic;
STAMP_var1,STAMP_var2,STAMP_var3 : out integer range 0 to N-1;
matrix_out : out MATRIX;
Z: out TYPE_IO);

end numberINsorting;

architecture BEHVnumberINsorting of numberINsorting is

signal ved: TYPE_IO ;
signal jala: TYPE_IO ;
-------------------------------------
--signal matrix_signal : MATRIX := (
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0') );
----------------

begin

dataIN : process(clock,Reset)

variable count : integer range 0 to (N-1) ;
------------------------------------------------
-----------------------------------------------
begin
----------------------------------------------

if reset='1' then
count:=0;

else if rising_edge(clock) then


if count=(N-1) then
count:=0;
else
count:=count +1;
end if;

ved(count)<= in_ved;
--jala(count) <= in_jala;
end if ;
end if;
end process dataIN;

----------SORTING STARTS HERE----------

sorting : process(ved)

variable list : TYPE_IO ;
variable tmp : std_logic_vector(M-1 downto 0);
begin

list := ved;

for i in 0 to N-2 loop
for j in 0 to N-2-i loop
if list(j+1) > list(j) then -- compare the two neighbors
tmp := list(j); -- swap a[j] and a[j+1]
list(j) := list(j+1);
list(j+1) := tmp;
end if;
end loop;
end loop;
--Z <= list;
jala <= list ; ----- output array

end process sorting;

-------------SORTING ENDS HERE ----------
-----------------------------------------

-----------STAMPING STARTS HERE----------
stampingrocess (clock9x,reset)

variable STS,STS1,STS2 : Boolean;
variable var_temp,VAR_TEMP1,var_temp2 : integer range 0 to N-1:=0;

begin
if reset = '1' then
STS := FALSE;
var_temp := 0;
var_temp1 := 0;
var_temp2 := 0;
else if rising_edge(clock9x) then


--------------------R AND D stamp-------------------
for k in 0 to N-1 loop

STS := ( ved(k) = jala(N-1) ) ;
if STS = TRUE then
var_temp := (k) ;
STAMP_var1 <= var_temp;
end if ;

STS1 := ( ved(k) = jala(N-2) ) ;
if STS1 = TRUE then
var_temp1 := (k) ;
STAMP_var2 <= var_temp1 ;
end if ;

STS2 := ( ved(k) = jala(N-3) ) ;
if STS2 = TRUE then
var_temp2 := (k) ;
STAMP_var3 <= var_temp2 ;
end if ;

end loop ;
----------------R AND D----------------------


end if; --end reset

end if; -- end clock

end process stamping;

----------------MATRIX FORMATION------------

Matrix_formation : process (clock9x)
----------------
variable matrix_var : MATRIX := (
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0') );
----------------

begin
--if reset='1' then
--
-- matrix_signal <= (
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0')
-- );

--else if rising_edge(clock9x) then
--else
matrix_var(1,stamp_var1) := '1' ;

matrix_var(2,stamp_var2) := '1' ;

matrix_var(3,stamp_var1) := '1' ;
matrix_var(3,stamp_var2) := '1' ;

matrix_var(4,stamp_var3) := '1' ;

matrix_var(5,stamp_var1) := '1' ;
matrix_var(5,stamp_var3) := '1' ;

matrix_var(6,stamp_var2) := '1' ;
matrix_var(6,stamp_var3) := '1' ;

matrix_var(7,stamp_var1) := '1' ;
matrix_var(7,stamp_var2) := '1' ;
matrix_var(7,stamp_var3) := '1' ;

matrix_out <= matrix_var;

-- end if ;
-- end if ;
end process Matrix_formation ;

--matrix_out <= matrix_var;
-----------------------------------------------
end BEHVnumberINsorting;






--ROM ved

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use WORK.CONV.ALL;

entity romVED is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romVEDarch of romVED is
begin

process(ADDRESS)
begin
case (ADDRESS) is
when 0 => Q_rom <= "1111"; -- F
when 1 => Q_rom <= "0000"; -- 0
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0001"; -- 1
when 4 => Q_rom <= "1100"; -- C
when 5 => Q_rom <= "1101"; -- D
when 6 => Q_rom <= "0101"; -- 5
when 7 => Q_rom <= "1000"; -- 8


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;




library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity romJALA is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romJALAarch of romJALA is
begin

process(ADDRESS)
begin
case (ADDRESS) is

when 0 => Q_rom <= "1100"; -- C
when 1 => Q_rom <= "1101"; -- D
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0101"; -- 5
when 4 => Q_rom <= "1000"; -- 8
when 5 => Q_rom <= "1111"; -- F
when 6 => Q_rom <= "0001"; -- 1
when 7 => Q_rom <= "0000"; -- 0


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;


---counter9x

--Changes will have to be made when frame size will be increasing
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use WORK.CONV.ALL;


ENTITY counter9X IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
clock9x : OUT std_logic
);

END counter9X ;


ARCHITECTURE arch_counter9X OF counter9X IS
BEGIN

-----------------------------------------
p0: process(clk,reset)

variable clk_var : std_logic;
--variable count : natural range 0 to 15;
variable count : integer range 0 to 17;
begin
if rising_edge(clk) then
if reset='1' then
clk_var :='0';
count:=0;
else
--------------------------------------
if count <= 8 or count >10 then
-- if count <= 13 or count > 15 then

-------------------------------------
clk_var :='0' ;
else
clk_var :='1' ;
end if;
clock9x <= clk_var;
if count=17 then
count:=0;
else
count:=count +1;
end if;

end if;

end if;
end process;

-----------------------------------------
END arch_counter9X;

---- counterFOR_rom

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use WORK.CONV.ALL;

entity counterForROM is
port (
CLK : in std_logic;
CLR : in std_logic;

Q : out integer range 0 to N-1
);
end entity;

library IEEE;
use IEEE.std_logic_unsigned.all;

architecture counterForROM_arch of counterForROM is

signal TEMP_Q : integer range 0 to N-1 ;


begin

process(CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
TEMP_Q <= 0;

else
if (TEMP_Q = N-1) then
TEMP_Q <= 0;
else
TEMP_Q <= TEMP_Q + 1;
end if;
end if;
Q <= TEMP_Q;
end if;


end process;

end architecture;

 

Thanks Duane.
Your comment helped me to sought out the problem.

I am again posting the whole code with previous problem rectified, but
with a new problem.

If you Guru's simulate all the files which I have provided, you will
find that the OUTPUT "matrix_output" (BASIC PROGRAM below) is
having a value 0080808080808080 latched since beginning, and these
latched values does not get removed.
Please point out the problem.

Thanks in advance.


--TOP LEVEL


library IEEE;
use IEEE.std_logic_1164.all;


entity numberINsorting_TB is
port(
CLOCK : in STD_LOGIC;
Reset : in STD_LOGIC
);
end numberINsorting_TB;

architecture numberINsorting_TB of numberINsorting_TB is

---- Component declarations -----

component counterForROM
port (
CLK : in STD_LOGIC;
CLR : in STD_LOGIC;
Q : out INTEGER range 0 to N-1
);
end component;
component numberINsorting
port (
Reset : in STD_LOGIC;
clock : in STD_LOGIC;
in_jala : in STD_LOGIC_VECTOR(M-1 downto 0);
in_ved : in STD_LOGIC_VECTOR(M-1 downto 0);
Z : out TYPE_IO
);
end component;
component romJALA
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;
component romVED
port (
ADDRESS : in INTEGER range 0 to N-1;
Q_rom : out STD_LOGIC_VECTOR(M-1 downto 0)
);
end component;

---- Signal declarations used on the diagram ----

signal NET169 : INTEGER range 0 to N-1;
signal BUS56 : STD_LOGIC_VECTOR (7 downto 0);
signal BUS67 : STD_LOGIC_VECTOR (7 downto 0);

begin

---- Component instantiations ----

U1 : numberINsorting
port map(
Reset => Reset,
clock => CLOCK,
in_jala => BUS67( 7 downto 0 ),
in_ved => BUS56( 7 downto 0 )
);

U2 : romJALA
port map(
ADDRESS => NET169,
Q_rom => BUS67( 7 downto 0 )
);

U3 : romVED
port map(
ADDRESS => NET169,
Q_rom => BUS56( 7 downto 0 )
);

U4 : counterForROM
port map(
CLK => CLOCK,
CLR => Reset,
Q => NET169
);


end numberINsorting_TB;





---- Basic program

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity numberINsorting is

port( in_ved: in std_logic_vector(M-1 downto 0);
in_jala: in std_logic_vector(M-1 downto 0);
clock,Reset,clock9x: in std_logic;
STAMP_var1,STAMP_var2,STAMP_var3 : out integer range 0 to N-1;
matrix_out : out MATRIX;
Z: out TYPE_IO);

end numberINsorting;

architecture BEHVnumberINsorting of numberINsorting is

signal ved: TYPE_IO ;
signal jala: TYPE_IO ;
-------------------------------------
--signal matrix_signal : MATRIX := (
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0') );
----------------

begin

dataIN : process(clock,Reset)

variable count : integer range 0 to (N-1) ;
------------------------------------------------
-----------------------------------------------
begin
----------------------------------------------

if reset='1' then
count:=0;

else if rising_edge(clock) then


if count=(N-1) then
count:=0;
else
count:=count +1;
end if;

ved(count)<= in_ved;
--jala(count) <= in_jala;
end if ;
end if;
end process dataIN;

----------SORTING STARTS HERE----------

sorting : process(ved)

variable list : TYPE_IO ;
variable tmp : std_logic_vector(M-1 downto 0);
begin

list := ved;

for i in 0 to N-2 loop
for j in 0 to N-2-i loop
if list(j+1) > list(j) then -- compare the two neighbors
tmp := list(j); -- swap a[j] and a[j+1]
list(j) := list(j+1);
list(j+1) := tmp;
end if;
end loop;
end loop;
--Z <= list;
jala <= list ; ----- output array

end process sorting;

-------------SORTING ENDS HERE ----------
-----------------------------------------

-----------STAMPING STARTS HERE----------
stampingrocess (clock9x,reset)

variable STS,STS1,STS2 : Boolean;
variable var_temp,VAR_TEMP1,var_temp2 : integer range 0 to N-1:=0;

begin
if reset = '1' then
STS := FALSE;
var_temp := 0;
var_temp1 := 0;
var_temp2 := 0;
else if rising_edge(clock9x) then


--------------------R AND D stamp-------------------
for k in 0 to N-1 loop

STS := ( ved(k) = jala(N-1) ) ;
if STS = TRUE then
var_temp := (k) ;
STAMP_var1 <= var_temp;
end if ;

STS1 := ( ved(k) = jala(N-2) ) ;
if STS1 = TRUE then
var_temp1 := (k) ;
STAMP_var2 <= var_temp1 ;
end if ;

STS2 := ( ved(k) = jala(N-3) ) ;
if STS2 = TRUE then
var_temp2 := (k) ;
STAMP_var3 <= var_temp2 ;
end if ;

end loop ;
----------------R AND D----------------------


end if; --end reset

end if; -- end clock

end process stamping;

----------------MATRIX FORMATION------------

Matrix_formation : process (clock9x)
----------------
variable matrix_var : MATRIX := (
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0'),
('0','0','0','0','0','0','0','0') );
----------------

begin
--if reset='1' then
--
-- matrix_signal <= (
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0'),
-- ('0','0','0','0','0','0','0','0')
-- );

--else if rising_edge(clock9x) then
--else
matrix_var(1,stamp_var1) := '1' ;

matrix_var(2,stamp_var2) := '1' ;

matrix_var(3,stamp_var1) := '1' ;
matrix_var(3,stamp_var2) := '1' ;

matrix_var(4,stamp_var3) := '1' ;

matrix_var(5,stamp_var1) := '1' ;
matrix_var(5,stamp_var3) := '1' ;

matrix_var(6,stamp_var2) := '1' ;
matrix_var(6,stamp_var3) := '1' ;

matrix_var(7,stamp_var1) := '1' ;
matrix_var(7,stamp_var2) := '1' ;
matrix_var(7,stamp_var3) := '1' ;

matrix_out <= matrix_var;

-- end if ;
-- end if ;
end process Matrix_formation ;

--matrix_out <= matrix_var;
-----------------------------------------------
end BEHVnumberINsorting;






--ROM ved

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use WORK.CONV.ALL;

entity romVED is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romVEDarch of romVED is
begin

process(ADDRESS)
begin
case (ADDRESS) is
when 0 => Q_rom <= "1111"; -- F
when 1 => Q_rom <= "0000"; -- 0
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0001"; -- 1
when 4 => Q_rom <= "1100"; -- C
when 5 => Q_rom <= "1101"; -- D
when 6 => Q_rom <= "0101"; -- 5
when 7 => Q_rom <= "1000"; -- 8


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;




library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--use IEEE.STD_LOGIC_SIGNED.ALL;
use WORK.CONV.ALL;

entity romJALA is
port (
ADDRESS : in integer range 0 to N-1;
Q_rom : out std_logic_vector(M-1 downto 0)
);
end entity;



library IEEE;
use IEEE.std_logic_unsigned.all;

architecture romJALAarch of romJALA is
begin

process(ADDRESS)
begin
case (ADDRESS) is

when 0 => Q_rom <= "1100"; -- C
when 1 => Q_rom <= "1101"; -- D
when 2 => Q_rom <= "0011"; -- 3
when 3 => Q_rom <= "0101"; -- 5
when 4 => Q_rom <= "1000"; -- 8
when 5 => Q_rom <= "1111"; -- F
when 6 => Q_rom <= "0001"; -- 1
when 7 => Q_rom <= "0000"; -- 0


--when others => Q_rom <= "0000";
end case;
end process;
end architecture;


---counter9x

--Changes will have to be made when frame size will be increasing
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
use WORK.CONV.ALL;


ENTITY counter9X IS
PORT(
clk : IN std_logic;
reset : IN std_logic;
clock9x : OUT std_logic
);

END counter9X ;


ARCHITECTURE arch_counter9X OF counter9X IS
BEGIN

-----------------------------------------
p0: process(clk,reset)

variable clk_var : std_logic;
--variable count : natural range 0 to 15;
variable count : integer range 0 to 17;
begin
if rising_edge(clk) then
if reset='1' then
clk_var :='0';
count:=0;
else
--------------------------------------
if count <= 8 or count >10 then
-- if count <= 13 or count > 15 then

-------------------------------------
clk_var :='0' ;
else
clk_var :='1' ;
end if;
clock9x <= clk_var;
if count=17 then
count:=0;
else
count:=count +1;
end if;

end if;

end if;
end process;

-----------------------------------------
END arch_counter9X;

---- counterFOR_rom

library WORK,IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

use WORK.CONV.ALL;

entity counterForROM is
port (
CLK : in std_logic;
CLR : in std_logic;

Q : out integer range 0 to N-1
);
end entity;

library IEEE;
use IEEE.std_logic_unsigned.all;

architecture counterForROM_arch of counterForROM is

signal TEMP_Q : integer range 0 to N-1 ;


begin

process(CLK)
begin
if rising_edge(CLK) then
if CLR = '1' then
TEMP_Q <= 0;

else
if (TEMP_Q = N-1) then
TEMP_Q <= 0;
else
TEMP_Q <= TEMP_Q + 1;
end if;
end if;
Q <= TEMP_Q;
end if;


end process;

end architecture;