problem of Indistinguishable faults

F

Fazela

Guest
Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.

I have a circuit connection like this.

--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|


Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not reported to be equivalent, but are
alwayd reported simulataneously as possible candidates when one of the
faults are inserted.

Is there some possible solution to this situation?

Thanks,
Fazela
 
Hello Fazela.

This is the case, it seems, because the same set of inputs will detect
both faults. Here's how:

OR-B-stuck-at-0:

- our objective is to propagate the B-input of the OR gate to the
output of the AND
gate.
- set OR(A) = 0, OR(B) = 1; NAND(A) = 0, NAND(B) = 0;
- If there is a fault, output of AND is 0, else it is 1.

NAND-B-stuck-at-1:
- our objective is to propagate the B-input of the NAND gate to the
output of the AND-gate
- set OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0;
- if there is a fault, output of AND is 0, else it is 1.

Pattern Summary:

OR@0 : OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;
NAND@1: OR(A) = 0; OR(B)= 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;

The tool is doing the right thing by using the same pattern to detect
both faults! its saving on patterns.

For NAND-B case, you COULD set both OR(A) and OR(B) to 1 (all we want
is output of OR gate to be 1) and get a new pattern.

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

Hope that helps.

Aditya

Fazela wrote:
Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.

I have a circuit connection like this.

--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|


Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not reported to be equivalent, but are
alwayd reported simulataneously as possible candidates when one of the
faults are inserted.

Is there some possible solution to this situation?

Thanks,
Fazela
Click to expand...
 
Hi Aditya,
I dont know if I completely understand the pattern combinations.
The whole trouble is because OR(A) = NAND(B) = n1 and OR(B) = NAND(A) =
n2.
So the pattern that you suggest:

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;
Click to expand...
will contradict at the inputs.

Thanks,
Fazela


Aditya Ramachandran wrote:
Hello Fazela.

This is the case, it seems, because the same set of inputs will detect
both faults. Here's how:

OR-B-stuck-at-0:

- our objective is to propagate the B-input of the OR gate to the
output of the AND
gate.
- set OR(A) = 0, OR(B) = 1; NAND(A) = 0, NAND(B) = 0;
- If there is a fault, output of AND is 0, else it is 1.

NAND-B-stuck-at-1:
- our objective is to propagate the B-input of the NAND gate to the
output of the AND-gate
- set OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0;
- if there is a fault, output of AND is 0, else it is 1.

Pattern Summary:

OR@0 : OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;
NAND@1: OR(A) = 0; OR(B)= 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;

The tool is doing the right thing by using the same pattern to detect
both faults! its saving on patterns.

For NAND-B case, you COULD set both OR(A) and OR(B) to 1 (all we want
is output of OR gate to be 1) and get a new pattern.

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

Hope that helps.

Aditya

Fazela wrote:
Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.

I have a circuit connection like this.

--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|


Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not reported to be equivalent, but are
alwayd reported simulataneously as possible candidates when one of the
faults are inserted.

Is there some possible solution to this situation?

Thanks,
Fazela
Click to expand...
 
Hello Fazela.

This can be worked out in the same way.

For OR(A) = NAND(B) = n1 stuck at 1:

n1 = 0; n2 = 1; if fault, out = 0 else out = 1

For OR(B) = NAND(A) = n2 stuck at 0:

n1 = 0; n2 = 1; if fault, out = 0 else out = 1

Same pattern works for both. However, see the other cases below:

Inputs | outputs in each case
n1 n2 | normal_circuit n1-sa-1 n2-sa-0
0 0 | 0 1 0
1 0 | 1 1 1
1 1 | 0 0 1

to distinguish between the faults do this:

1. apply n1, n2 = 00, if you get 1 there is n1-sa-1 fault else there
isnt one.
( there is no guarantee that n2-sa-0 does not exist)
2. then apply n1,n2 = 11, if you get 0 there is no n2-sa-0 fault else
there is one.
(this pattern ALONE does not guarantee absence of n1-sa-1 fault)
3. if both pass, neither fault exists.

point is by applying n1,n2 =01 both faults cause a 0 while normal
circuit returns
a 1. two birds with one stone etc. thats what the tool is trying to do,
i think.

Aditya

Fazela wrote:
Hi Aditya,
I dont know if I completely understand the pattern combinations.
The whole trouble is because OR(A) = NAND(B) = n1 and OR(B) = NAND(A) =
n2.
So the pattern that you suggest:

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

will contradict at the inputs.

Thanks,
Fazela


Aditya Ramachandran wrote:
Hello Fazela.

This is the case, it seems, because the same set of inputs will detect
both faults. Here's how:

OR-B-stuck-at-0:

- our objective is to propagate the B-input of the OR gate to the
output of the AND
gate.
- set OR(A) = 0, OR(B) = 1; NAND(A) = 0, NAND(B) = 0;
- If there is a fault, output of AND is 0, else it is 1.

NAND-B-stuck-at-1:
- our objective is to propagate the B-input of the NAND gate to the
output of the AND-gate
- set OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0;
- if there is a fault, output of AND is 0, else it is 1.

Pattern Summary:

OR@0 : OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;
NAND@1: OR(A) = 0; OR(B)= 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;

The tool is doing the right thing by using the same pattern to detect
both faults! its saving on patterns.

For NAND-B case, you COULD set both OR(A) and OR(B) to 1 (all we want
is output of OR gate to be 1) and get a new pattern.

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

Hope that helps.

Aditya

Fazela wrote:
Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.

I have a circuit connection like this.

--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|


Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not reported to be equivalent, but are
alwayd reported simulataneously as possible candidates when one of the
faults are inserted.

Is there some possible solution to this situation?

Thanks,
Fazela
Click to expand...
 
Hi Aditya,
I just had this comment:

1. apply n1, n2 = 00, if you get 1 there is n1-sa-1 fault else there
isnt one.
( there is no guarantee that n2-sa-0 does not exist)
Click to expand...
n1 is sa1 at the B input of the NAND gate. If we apply n1n2 = 00 ,
output of the OR gate becomes 0 and hence the output of AND gate
becomes 0. So whatever is propagated from the NAND gate side is almost.

Similarly if we make n1n2 = 11, for n2 sa0 at the OR gate, output of
NAND gate becomes 0 and hence that of the AND gate.

Thanks,
Fazela

Aditya Ramachandran wrote:
Hello Fazela.

This can be worked out in the same way.

For OR(A) = NAND(B) = n1 stuck at 1:

n1 = 0; n2 = 1; if fault, out = 0 else out = 1

For OR(B) = NAND(A) = n2 stuck at 0:

n1 = 0; n2 = 1; if fault, out = 0 else out = 1

Same pattern works for both. However, see the other cases below:

Inputs | outputs in each case
n1 n2 | normal_circuit n1-sa-1 n2-sa-0
0 0 | 0 1 0
1 0 | 1 1 1
1 1 | 0 0 1

to distinguish between the faults do this:

1. apply n1, n2 = 00, if you get 1 there is n1-sa-1 fault else there
isnt one.
( there is no guarantee that n2-sa-0 does not exist)
2. then apply n1,n2 = 11, if you get 0 there is no n2-sa-0 fault else
there is one.
(this pattern ALONE does not guarantee absence of n1-sa-1 fault)
3. if both pass, neither fault exists.

point is by applying n1,n2 =01 both faults cause a 0 while normal
circuit returns
a 1. two birds with one stone etc. thats what the tool is trying to do,
i think.

Aditya

Fazela wrote:
Hi Aditya,
I dont know if I completely understand the pattern combinations.
The whole trouble is because OR(A) = NAND(B) = n1 and OR(B) = NAND(A) =
n2.
So the pattern that you suggest:

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

will contradict at the inputs.

Thanks,
Fazela


Aditya Ramachandran wrote:
Hello Fazela.

This is the case, it seems, because the same set of inputs will detect
both faults. Here's how:

OR-B-stuck-at-0:

- our objective is to propagate the B-input of the OR gate to the
output of the AND
gate.
- set OR(A) = 0, OR(B) = 1; NAND(A) = 0, NAND(B) = 0;
- If there is a fault, output of AND is 0, else it is 1.

NAND-B-stuck-at-1:
- our objective is to propagate the B-input of the NAND gate to the
output of the AND-gate
- set OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0;
- if there is a fault, output of AND is 0, else it is 1.

Pattern Summary:

OR@0 : OR(A) = 0; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;
NAND@1: OR(A) = 0; OR(B)= 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT =
1;

The tool is doing the right thing by using the same pattern to detect
both faults! its saving on patterns.

For NAND-B case, you COULD set both OR(A) and OR(B) to 1 (all we want
is output of OR gate to be 1) and get a new pattern.

OR(A) = 1; OR(B) = 1; NAND(A) = 0; NAND(B) = 0; CORRECT_OUTPUT = 1;

Hope that helps.

Aditya

Fazela wrote:
Hello All,
I am running ATPG on some test benchmark circuits and I have come
across this strange scenario and so I was wondering if someone could
comment on it.

I have a circuit connection like this.

--n1----|A----------|
| OR |---n3----|
--n2---|B-----------| |
|-------|----------|
| AND |----n5---
|--------|----------|
|
--n2---|A------------| |
| NAND |---n4--|
--n1---|B------------|


Now there exists a "stuck at 0" fault on B input of the OR gate and a
"stuck at 1" fault on the B input of NAND gate. In this case whatever
patterns we try to apply both these faults are always detected
simultaneuosly. I mean they are not reported to be equivalent, but are
alwayd reported simulataneously as possible candidates when one of the
faults are inserted.

Is there some possible solution to this situation?

Thanks,
Fazela
Click to expand...
 
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