Problem instantiating xilinx blockram ramb4_s1_s16

F

Frank Benoit

Guest
Hi

I have problems instantiating the ramb4_s1_s16 in vhdl. ramb4_s2_s16 works
fine. The error message is
....
=========================================================================
* Low Level Synthesis *
=========================================================================
ERROR:Xst:79 - Model 'RAMB4_S1_S16' has different characteristics in
destination library
ERROR:Xst:1831 - Missing ports are:DOA0 DIA0 ERROR:Xst:1832 - Unknown
ports are:DOA DIA ERROR: XST failed
Process "Synthesize" did not complete.


Following I have listed my test code for both blockrams.
Can anybody show me what I missed?

Frank


/////////////////////////////////////////////////////////////////////////////
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity testram2 is
port (
DOA : out STD_LOGIC_VECTOR (0 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
ADDRA : in STD_LOGIC_VECTOR (11 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (0 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
RSTA : in STD_ULOGIC;
RSTB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC );
end testram2;

architecture Behavioral of testram2 is
component RAMB4_S1_S16
port (
DOA : out STD_LOGIC_VECTOR (0 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
ADDRA : in STD_LOGIC_VECTOR (11 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (0 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
RSTA : in STD_ULOGIC;
RSTB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC );
end component;

begin
ram0 : RAMB4_S1_S16
port map(
CLKA => CLKA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
ENA => ENA,
RSTA => RSTA,
CLKB => CLKB,
WEB => WEB,
ADDRB => ADDRB,
DIB => DIB,
DOB => DOB,
ENB => ENB,
RSTB => RSTB
);


end Behavioral;
///////////////////////////////////////////////////////////////

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity testram is
port (
DOA : out STD_LOGIC_VECTOR (1 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
ADDRA : in STD_LOGIC_VECTOR (10 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (1 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
RSTA : in STD_ULOGIC;
RSTB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC );
end testram;

architecture Behavioral of testram is
component RAMB4_S2_S16
port (
DOA : out STD_LOGIC_VECTOR (1 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
ADDRA : in STD_LOGIC_VECTOR (10 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (1 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
RSTA : in STD_ULOGIC;
RSTB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC );
end component;
begin

ram0 : RAMB4_S2_S16
port map(
CLKA => CLKA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
ENA => ENA,
RSTA => RSTA,
CLKB => CLKB,
WEB => WEB,
ADDRB => ADDRB,
DIB => DIB,
DOB => DOB,
ENB => ENB,
RSTB => RSTB
);

end Behavioral;
 
Now I tried it with ISE BaseX and it worked.
With ISE Webpack it doesn't.
In both cases I used the spartan 2 xc2s50. It should work with webpack to!
What going wrong?

Frank
 
Frank Benoit wrote:
Now I tried it with ISE BaseX and it worked.
With ISE Webpack it doesn't.
In both cases I used the spartan 2 xc2s50. It should work with webpack to!
What going wrong?

Frank
Click to expand...
I don't know if this will fix your problem or not but I highly suggest
you uncomment the UNISIM library declaration and get rid of the
component declaration. When I do that, it gets rid of all of the
warnings in XST when I try this code. Not only does it get rid of
unnecessary warnings but these changes are necessary if you plan to
simulate this code and it should clean up the hierarchy tree in the
Project Navigator view as well. Try this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
library UNISIM;
use UNISIM.VComponents.all;

entity testram2 is
port (
DOA : out STD_LOGIC_VECTOR (0 downto 0);
DOB : out STD_LOGIC_VECTOR (15 downto 0);
ADDRA : in STD_LOGIC_VECTOR (11 downto 0);
ADDRB : in STD_LOGIC_VECTOR (7 downto 0);
CLKA : in STD_ULOGIC;
CLKB : in STD_ULOGIC;
DIA : in STD_LOGIC_VECTOR (0 downto 0);
DIB : in STD_LOGIC_VECTOR (15 downto 0);
ENA : in STD_ULOGIC;
ENB : in STD_ULOGIC;
RSTA : in STD_ULOGIC;
RSTB : in STD_ULOGIC;
WEA : in STD_ULOGIC;
WEB : in STD_ULOGIC );
end testram2;

architecture Behavioral of testram2 is
begin
ram0 : RAMB4_S1_S16
port map(
CLKA => CLKA,
WEA => WEA,
ADDRA => ADDRA,
DIA => DIA,
DOA => DOA,
ENA => ENA,
RSTA => RSTA,
CLKB => CLKB,
WEB => WEB,
ADDRB => ADDRB,
DIB => DIB,
DOB => DOB,
ENB => ENB,
RSTB => RSTB
);

end Behavioral;
 
Thanks for your answer

I think I tried it like that too. But I will try it again tomorrow in
office.

I spent 2 days with that problem. And then on my other office
where I have a BaseX it worked. What a shock.
So, I think the problem is in the webpack, not in the code?
But I need it working on the place with the ISE webpack.

Frank
 
Frank Benoit wrote:
Thanks for your answer

I think I tried it like that too. But I will try it again tomorrow in
office.

I spent 2 days with that problem. And then on my other office
where I have a BaseX it worked. What a shock.
So, I think the problem is in the webpack, not in the code?
But I need it working on the place with the ISE webpack.

Frank
Click to expand...

XST in the WebPack is the same as XST in Base-X to my knowledge. If you
have the same versions including service pack, I can not think of any
reason why the two would act differently in this respect. I have seen a
few strange things in the past like a hidden control character in the
code or left over "garbage" from a previous run in the working directory
cause situations like this. You might want to take another look at the
code and/or try creating a new project directory in the WebPack software
to see if it changes anything for you. May help you track down the problem.

-- Brian
 
On Thu, 12 Aug 2004 16:04:44 -0600, Brian Philofsky wrote:

XST in the WebPack is the same as XST in Base-X to my knowledge. If you
have the same versions including service pack, I can not think of any
reason why the two would act differently in this respect. I have seen a
few strange things in the past like a hidden control character in the code
or left over "garbage" from a previous run in the working directory cause
situations like this. You might want to take another look at the code
and/or try creating a new project directory in the WebPack software to see
if it changes anything for you. May help you track down the problem.

-- Brian
Click to expand...
You were right. I tried a new project and it works.
Thank you for the tips.

Frank
 
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