problem in timing simulation

Hi all,

The following piece of code works in functional simulation
--*************************************************************************
--This process is used to detect the start condition(I2C).
-- SDA is used as the clock for this purpose
--*************************************************************************
process(sda,sys_reset,current_i2c_state,scl)
begin
if(sys_reset='0' or current_i2c_state= I2C_HEADER)then
detect_start <= '0';
elsif(sda='0' and sda'event)then
if(scl/= '0')then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end process;

--**********************************************************--

In functional sim it works fine but when i do the timing simulation
even when the condition is satisfied the detct_start dosen't go high.

Note: This is the start detction logic for I2C .Since SCL and SDA are
externally pulled up '1' is converted to a 'Z'(not shown here).
the sda will aways be either '0' or 'Z' never a '1'.
But same is the case for funstional simulation.

I am using modelsim simuator to perform timing simulation .
and industry standard delay file(SDO format) generated by altera.

Any suggestions appreciated.

Thanks in advance,
Praveen

 

[Hubble]

Why do you use current_i2c_state in the async part. My impression is
that this shoud be an async reset and all other things, especially the
state (!) in the sync part:

process(sda,sys_reset) -- only clock, reset here
begin
if(sys_reset='0' )then
detect_start <= '0';
elsif(sda='0' and sda'event)then
if current_i2c_state= I2C_HEADER then
detect_start <= '0';
elsif(scl/= '0')then
detect_start <= '1';
else
detect_start <= '0';
end if;
end if;
end process;

SCL and SDA are
externally pulled up '1' is converted to a 'Z'(not shown here).

You can drive 'H' from the test bench, so it will toggle 0 and H at
least.

Hubble.